arm: add smax/smin expanders for v*hf

This patch adds the missing expanders for smax/smin for v*hf modes,
by using the VDQWH iterator instead of VALLW.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/vec-common.md (smin<mode>3): Use VDQWH iterator.
	(smax<mode>3): Likewise.

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index b5fc86fdf28a61af0d32faeda0eb0d5b884c360a..6183c931e36b8bfb547a85eefe4fef2676f51fdc 100644 (file)
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -110,9 +110,9 @@
 )
 
 (define_expand "smin<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand")
-       (smin:VALLW (match_operand:VALLW 1 "s_register_operand")
-                   (match_operand:VALLW 2 "s_register_operand")))]
+  [(set (match_operand:VDQWH 0 "s_register_operand")
+       (smin:VDQWH (match_operand:VDQWH 1 "s_register_operand")
+                   (match_operand:VDQWH 2 "s_register_operand")))]
    "ARM_HAVE_<MODE>_ARITH"
 )
 
@@ -124,9 +124,9 @@
 )
 
 (define_expand "smax<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand")
-       (smax:VALLW (match_operand:VALLW 1 "s_register_operand")
-                   (match_operand:VALLW 2 "s_register_operand")))]
+  [(set (match_operand:VDQWH 0 "s_register_operand")
+       (smax:VDQWH (match_operand:VDQWH 1 "s_register_operand")
+                   (match_operand:VDQWH 2 "s_register_operand")))]
    "ARM_HAVE_<MODE>_ARITH"
 )