clk: samsung: exynosautov920: add block mfc clock support

Add support for CMU_MFC which provides clocks to MFC block, and
register the required compatible and cmu_info for the same.

Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
index 75deec8bece54272628945b7bb22dc5621a3dc68..b90b73c3518fe3f476e705433e03540ef389d6a7 100644 (file)
--- a/drivers/clk/samsung/clk-exynosautov920.c
+++ b/drivers/clk/samsung/clk-exynosautov920.c
@@ -28,6 +28,7 @@
 #define CLKS_NR_HSI1                   (CLK_MOUT_HSI1_USBDRD + 1)
 #define CLKS_NR_HSI2                   (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
 #define CLKS_NR_M2M                     (CLK_DOUT_M2M_NOCP + 1)
+#define CLKS_NR_MFC                     (CLK_DOUT_MFC_NOCP + 1)
 
 /* ---- CMU_TOP ------------------------------------------------------------ */
 
@@ -1863,6 +1864,47 @@ static const struct samsung_cmu_info m2m_cmu_info __initconst = {
        .clk_name               = "noc",
 };
 
+/* ---- CMU_MFC --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_MFC (0x19c00000) */
+#define PLL_CON0_MUX_CLKCMU_MFC_MFC_USER        0x600
+#define PLL_CON0_MUX_CLKCMU_MFC_WFD_USER        0x610
+#define CLK_CON_DIV_DIV_CLK_MFC_NOCP            0x1800
+
+static const unsigned long mfc_clk_regs[] __initconst = {
+       PLL_CON0_MUX_CLKCMU_MFC_MFC_USER,
+       PLL_CON0_MUX_CLKCMU_MFC_WFD_USER,
+       CLK_CON_DIV_DIV_CLK_MFC_NOCP,
+};
+
+/* List of parent clocks for Muxes in CMU_MFC */
+PNAME(mout_clkcmu_mfc_mfc_user_p) = { "oscclk", "dout_clkcmu_mfc_mfc" };
+PNAME(mout_clkcmu_mfc_wfd_user_p) = { "oscclk", "dout_clkcmu_mfc_wfd" };
+
+static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
+       MUX(CLK_MOUT_MFC_MFC_USER, "mout_clkcmu_mfc_mfc_user",
+           mout_clkcmu_mfc_mfc_user_p, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 4, 1),
+       MUX(CLK_MOUT_MFC_WFD_USER, "mout_clkcmu_mfc_wfd_user",
+           mout_clkcmu_mfc_wfd_user_p, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, 4, 1),
+};
+
+static const struct samsung_div_clock mfc_div_clks[] __initconst = {
+       DIV(CLK_DOUT_MFC_NOCP, "dout_mfc_nocp",
+           "mout_clkcmu_mfc_mfc_user", CLK_CON_DIV_DIV_CLK_MFC_NOCP,
+           0, 3),
+};
+
+static const struct samsung_cmu_info mfc_cmu_info __initconst = {
+       .mux_clks               = mfc_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(mfc_mux_clks),
+       .div_clks               = mfc_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(mfc_div_clks),
+       .nr_clk_ids             = CLKS_NR_MFC,
+       .clk_regs               = mfc_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(mfc_clk_regs),
+       .clk_name               = "noc",
+};
+
 static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
 {
        const struct samsung_cmu_info *info;
@@ -1896,6 +1938,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
        }, {
                .compatible = "samsung,exynosautov920-cmu-m2m",
                .data = &m2m_cmu_info,
+       }, {
+               .compatible = "samsung,exynosautov920-cmu-mfc",
+               .data = &mfc_cmu_info,
        },
        { }
 };