ARM: dts: microchip: add sama7d65 SoC DT

Add Device Tree for sama7d65 SoC.

Co-developed-by: Dharma Balasubiramani <dharma.b@microchip.com>
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Co-developed-by: Romain Sioen <romain.sioen@microchip.com>
Signed-off-by: Romain Sioen <romain.sioen@microchip.com>
Co-developed-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250107160850.120537-5-Ryan.Wanner@microchip.com
[claudiu.beznea: dropped comma typo from copyright, dropped space in
 front of slow_xtal node, dropped empty space after slow_xtal node]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
new file mode 100644 (file)
index 0000000..854b30d
--- /dev/null
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *  sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
+ *
+ *  Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ *  Author: Ryan Wanner <Ryan.Wanner@microchip.com>
+ *
+ */
+
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/at91-usart.h>
+
+/ {
+       model = "Microchip SAMA7D65 family SoC";
+       compatible = "microchip,sama7d65";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a7";
+                       reg = <0x0>;
+                       device_type = "cpu";
+                       clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
+                       clock-names = "cpu";
+               };
+       };
+
+       clocks {
+               main_xtal: clock-mainxtal {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+               };
+
+               slow_xtal: clock-slowxtal {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               ranges;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               pioa: pinctrl@e0014000 {
+                       compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
+                       reg = <0xe0014000 0x800>;
+                       interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               pmc: clock-controller@e0018000 {
+                       compatible = "microchip,sama7d65-pmc", "syscon";
+                       reg = <0xe0018000 0x200>;
+                       interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                       #clock-cells = <2>;
+                       clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+                       clock-names = "td_slck", "md_slck", "main_xtal";
+               };
+
+               clk32k: clock-controller@e001d500 {
+                       compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
+                       reg = <0xe001d500 0x4>;
+                       clocks = <&slow_xtal>;
+                       #clock-cells = <1>;
+               };
+
+               sdmmc1: mmc@e1208000 {
+                       compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
+                       reg = <0xe1208000 0x400>;
+                       interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
+                       clock-names = "hclock", "multclk";
+                       assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
+                       assigned-clock-rates = <200000000>;
+                       assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
+                       status = "disabled";
+               };
+
+               pit64b0: timer@e1800000 {
+                       compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
+                       reg = <0xe1800000 0x100>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
+                       clock-names = "pclk", "gclk";
+               };
+
+               pit64b1: timer@e1804000 {
+                       compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
+                       reg = <0xe1804000 0x100>;
+                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
+                       clock-names = "pclk", "gclk";
+               };
+
+               flx6: flexcom@e2020000 {
+                       compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
+                       reg = <0xe2020000 0x200>;
+                       ranges = <0x0 0xe2020000 0x800>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+                       status = "disabled";
+
+                       uart6: serial@200 {
+                               compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+                               reg = <0x200 0x200>;
+                               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+                               clock-names = "usart";
+                               atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+                               atmel,fifo-size = <16>;
+                               status = "disabled";
+                       };
+               };
+
+               gic: interrupt-controller@e8c11000 {
+                       compatible = "arm,cortex-a7-gic";
+                       reg = <0xe8c11000 0x1000>,
+                             <0xe8c12000 0x2000>;
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+               };
+       };
+};