[AArch64] Prefer error messages from opcodes enabled in CPU_VARIANT

Printing error messages from opcodes that would otherwise not be used
due to not being enabled is pointless when there are other
alternatives.  Prefer error messages from enabled opcodes instead.

A more ideal fix would to sort error messages earlier when deciding
which KIND to return.  That is, other fatal errors of a less serious
KIND from an enabled opcode should get priority over a more serious
KIND of a disabled opcode.

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (output_operand_error_report): Account
	for CPU_VARIANT in error messages.
	* testsuite/gas/aarch64/illegal-sve2.l: Adjust.
	* testsuite/gas/aarch64/verbose-error.l: Adjust.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4e394a2a25fc34274246563b1934ac6856563436..0a7e5796bb797090e826558e535fc6ab17e68e94 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * config/tc-aarch64.c (output_operand_error_report): Account
+       for CPU_VARIANT in error messages.
+       * testsuite/gas/aarch64/illegal-sve2.l: Adjust.
+       * testsuite/gas/aarch64/verbose-error.l: Adjust.
+
 2020-10-17  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/25878

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fac571ea5734d3fe741ba0dd0d66d288caf9d45f..37cf286f5e865dccef2099dbda32c4d16e3d134b 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4937,12 +4937,12 @@ output_operand_error_record (const operand_error_record *record, char *str)
 static void
 output_operand_error_report (char *str, bfd_boolean non_fatal_only)
 {
-  int largest_error_pos;
-  const char *msg = NULL;
+  int largest_error_pos, largest_error_pos2;
+  const char *msg = NULL, *msg2 = NULL;
   enum aarch64_operand_error_kind kind;
   operand_error_record *curr;
   operand_error_record *head = operand_error_report.head;
-  operand_error_record *record = NULL;
+  operand_error_record *record = NULL, *record2 = NULL;
 
   /* No error to report.  */
   if (head == NULL)
@@ -4980,6 +4980,7 @@ output_operand_error_report (char *str, bfd_boolean non_fatal_only)
 
   /* Pick up one of errors of KIND to report.  */
   largest_error_pos = -2; /* Index can be -1 which means unknown index.  */
+  largest_error_pos2 = -2; /* Index can be -1 which means unknown index.  */
   for (curr = head; curr != NULL; curr = curr->next)
     {
       /* If we don't want to print non-fatal errors then don't consider them
@@ -4991,16 +4992,39 @@ output_operand_error_report (char *str, bfd_boolean non_fatal_only)
         mismatching operand index.  In the case of multiple errors with
         the equally highest operand index, pick up the first one or the
         first one with non-NULL error message.  */
-      if (curr->detail.index > largest_error_pos
-         || (curr->detail.index == largest_error_pos && msg == NULL
-             && curr->detail.error != NULL))
+      if (AARCH64_CPU_HAS_FEATURE (cpu_variant, *curr->opcode->avariant))
        {
-         largest_error_pos = curr->detail.index;
-         record = curr;
-         msg = record->detail.error;
+         if (curr->detail.index > largest_error_pos
+             || (curr->detail.index == largest_error_pos && msg == NULL
+                 && curr->detail.error != NULL))
+           {
+             largest_error_pos = curr->detail.index;
+             record = curr;
+             msg = record->detail.error;
+           }
+       }
+      else
+       {
+         if (curr->detail.index > largest_error_pos2
+             || (curr->detail.index == largest_error_pos2 && msg2 == NULL
+                 && curr->detail.error != NULL))
+           {
+             largest_error_pos2 = curr->detail.index;
+             record2 = curr;
+             msg2 = record2->detail.error;
+           }
        }
     }
 
+  /* No errors in enabled cpu feature variants, look for errors in the disabled
+     ones.  XXX we should do this segregation when prioritizing too.  */
+  if (!record)
+    {
+      largest_error_pos = largest_error_pos2;
+      record = record2;
+      msg = msg2;
+    }
+
   /* The way errors are collected in the back-end is a bit non-intuitive.  But
      essentially, because each operand template is tried recursively you may
      always have errors collected from the previous tried OPND.  These are

diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 7656c2f91b19564aa65db4985562f9307f344769..fb875b8d967d59230e6a76e72da496e4d80b5553 100644 (file)
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -83,7 +83,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.h,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           bcax z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl z0\.d,z1\.d,z0\.d,z0\.d'
@@ -792,7 +792,7 @@
 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnt z32\.b,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnt z0\.b,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnt z0\.b,z0\.h,z32\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `rax1 z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rax1 z32\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rax1 z0\.d,z32\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rax1 z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `rax1 z0\.d,z0\.d,z0\.h'
@@ -1068,13 +1068,13 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 3 -- `sli z0\.d,z0\.d,#64'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sm4e z0\.s,z0\.s,z1\.s'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sm4e z1\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4e z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sm4e z32\.s,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4e z0\.s,z32\.s,z0\.s'
 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4e z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sm4e z0\.s,z0\.s,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sm4e z0\.s, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4ekey z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sm4ekey z32\.s,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4ekey z0\.s,z32\.s,z0\.s'
 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4ekey z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sm4ekey z0\.s,z0\.s,z0\.h'
@@ -1593,7 +1593,7 @@
 [^ :]+:[0-9]+: Info:           sqrdcmlah z0\.h, z0\.h, z0\.h, #0
 [^ :]+:[0-9]+: Info:           sqrdcmlah z0\.s, z0\.s, z0\.s, #0
 [^ :]+:[0-9]+: Info:           sqrdcmlah z0\.d, z0\.d, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlah z0\.h,z0\.h,z0\.h\[8\]'
@@ -1603,7 +1603,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlah z0\.s,z0\.s,z0\.s\[4\]'
@@ -1613,7 +1613,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlah z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlah z0\.d,z0\.d,z0\.d\[2\]'
@@ -1623,7 +1623,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlah z32\.h,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlah z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlah z0\.s,z0\.h,z0\.x'
@@ -1634,7 +1634,7 @@
 [^ :]+:[0-9]+: Info:           sqrdmlah z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:           sqrdmlah z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:           sqrdmlah z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z0\.h\[8\]'
@@ -1644,7 +1644,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z0\.s\[4\]'
@@ -1654,7 +1654,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z0\.d\[2\]'
@@ -1664,7 +1664,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:           sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlsh z0\.s,z0\.h,z0\.x'
@@ -3319,7 +3319,7 @@
 [^ :]+:[0-9]+: Info:           xar z0\.s, z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:           xar z0\.d, z0\.d, z0\.d, #1
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `xar z0\.b,z1\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `xar z32\.b,z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `xar z32\.b,z32\.b,z0\.b,#1'
 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `xar z0\.b,z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#9'

diff --git a/gas/testsuite/gas/aarch64/verbose-error.l b/gas/testsuite/gas/aarch64/verbose-error.l
index 5696a5c46710451430ccd070f8643dd0d5f7825a..77d83c4b39a285808d1df784598f43e8cedc5ec6 100644 (file)
--- a/gas/testsuite/gas/aarch64/verbose-error.l
+++ b/gas/testsuite/gas/aarch64/verbose-error.l
@@ -67,9 +67,10 @@
 [^:]*:22: Info:        rev32 v4.8h, v5.8h
 [^:]*:24: Error: operand mismatch -- `frintn v6.8b,v7.8b'
 [^:]*:24: Info:    did you mean this\?
-[^:]*:24: Info:        frintn v6.4h, v7.4h
+[^:]*:24: Info:        frintn v6.2s, v7.2s
 [^:]*:24: Info:    other valid variant\(s\):
-[^:]*:24: Info:        frintn v6.8h, v7.8h
+[^:]*:24: Info:        frintn v6.4s, v7.4s
+[^:]*:24: Info:        frintn v6.2d, v7.2d
 [^:]*:26: Error: operand mismatch -- `rev64 v8.2d,v9.2d'
 [^:]*:26: Info:    did you mean this\?
 [^:]*:26: Info:        rev64 v8.8b, v9.8b