arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528

Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
doesn't provide a separate MSI controller, thus the one integrated in
designware PCIe IP must be used.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://patch.msgid.link/20250918153057.56023-3-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index d5f8f7b9bf019198179d8d42f04ad7079ce5b426..d402f282881428fb95ca887715894ce0c1316e3c 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
 #include <dt-bindings/power/rockchip,rk3528-power.h>
@@ -278,10 +279,63 @@
 
        soc {
                compatible = "simple-bus";
-               ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
+               ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
                #address-cells = <2>;
                #size-cells = <2>;
 
+               pcie: pcie@fe000000 {
+                       compatible = "rockchip,rk3528-pcie",
+                                    "rockchip,rk3568-pcie";
+                       reg = <0x0 0xfe000000 0x0 0x400000>,
+                             <0x0 0xfe4f0000 0x0 0x010000>,
+                             <0x0 0xfc000000 0x0 0x100000>;
+                       reg-names = "dbi", "apb", "config";
+                       bus-range = <0x0 0xff>;
+                       clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
+                                <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
+                                <&cru CLK_PCIE_AUX>;
+                       clock-names = "aclk_mst", "aclk_slv",
+                                     "aclk_dbi", "pclk",
+                                     "aux";
+                       device_type = "pci";
+                       interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+                                         "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc 0>,
+                                       <0 0 0 2 &pcie_intc 1>,
+                                       <0 0 0 3 &pcie_intc 2>,
+                                       <0 0 0 4 &pcie_intc 3>;
+                       linux,pci-domain = <0>;
+                       max-link-speed = <2>;
+                       num-lanes = <1>;
+                       phys = <&combphy PHY_TYPE_PCIE>;
+                       phy-names = "pcie-phy";
+                       power-domains = <&power RK3528_PD_VPU>;
+                       ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
+                                <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
+                                <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
+                       resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
+                       reset-names = "pwr", "pipe";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       status = "disabled";
+
+                       pcie_intc: legacy-interrupt-controller {
+                               interrupt-controller;
+                               interrupt-parent = <&gic>;
+                               interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
                gic: interrupt-controller@fed01000 {
                        compatible = "arm,gic-400";
                        reg = <0x0 0xfed01000 0 0x1000>,