--- /dev/null
+From e701156ccc6c7a5f104a968dda74cd6434178712 Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Fri, 7 Jul 2023 21:26:09 -0500
+Subject: drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation with SMU13
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+commit e701156ccc6c7a5f104a968dda74cd6434178712 upstream.
+
+SMU13 overrides dynamic PCIe lane width and dynamic speed by when on
+certain hosts. commit 38e4ced80479 ("drm/amd/pm: conditionally disable
+pcie lane switching for some sienna_cichlid SKUs") worked around this
+issue by setting up certain SKUs to set up certain limits, but the same
+fundamental problem with those hosts affects all SMU11 implmentations
+as well, so align the SMU11 and SMU13 driver handling.
+
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.1.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 89 ++++---------------
+ 1 file changed, 18 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+index 8fe2e1716da4..f6599c00a6fd 100644
+--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+@@ -2077,89 +2077,36 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
+ return ret;
+ }
+
+-static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu,
+- uint32_t *gen_speed_override,
+- uint32_t *lane_width_override)
+-{
+- struct amdgpu_device *adev = smu->adev;
+-
+- *gen_speed_override = 0xff;
+- *lane_width_override = 0xff;
+-
+- switch (adev->pdev->device) {
+- case 0x73A0:
+- case 0x73A1:
+- case 0x73A2:
+- case 0x73A3:
+- case 0x73AB:
+- case 0x73AE:
+- /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */
+- *lane_width_override = 6;
+- break;
+- case 0x73E0:
+- case 0x73E1:
+- case 0x73E3:
+- *lane_width_override = 4;
+- break;
+- case 0x7420:
+- case 0x7421:
+- case 0x7422:
+- case 0x7423:
+- case 0x7424:
+- *lane_width_override = 3;
+- break;
+- default:
+- break;
+- }
+-}
+-
+-#define MAX(a, b) ((a) > (b) ? (a) : (b))
+-
+ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
+ uint32_t pcie_gen_cap,
+ uint32_t pcie_width_cap)
+ {
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
+- uint32_t gen_speed_override, lane_width_override;
+- uint8_t *table_member1, *table_member2;
+- uint32_t min_gen_speed, max_gen_speed;
+- uint32_t min_lane_width, max_lane_width;
+- uint32_t smu_pcie_arg;
++ u32 smu_pcie_arg;
+ int ret, i;
+
+- GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
+- GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
+-
+- sienna_cichlid_get_override_pcie_settings(smu,
+- &gen_speed_override,
+- &lane_width_override);
++ /* PCIE gen speed and lane width override */
++ if (!amdgpu_device_pcie_dynamic_switching_supported()) {
++ if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap)
++ pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1];
+
+- /* PCIE gen speed override */
+- if (gen_speed_override != 0xff) {
+- min_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
+- max_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
+- } else {
+- min_gen_speed = MAX(0, table_member1[0]);
+- max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
+- min_gen_speed = min_gen_speed > max_gen_speed ?
+- max_gen_speed : min_gen_speed;
+- }
+- pcie_table->pcie_gen[0] = min_gen_speed;
+- pcie_table->pcie_gen[1] = max_gen_speed;
++ if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap)
++ pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1];
+
+- /* PCIE lane width override */
+- if (lane_width_override != 0xff) {
+- min_lane_width = MIN(pcie_width_cap, lane_width_override);
+- max_lane_width = MIN(pcie_width_cap, lane_width_override);
++ /* Force all levels to use the same settings */
++ for (i = 0; i < NUM_LINK_LEVELS; i++) {
++ pcie_table->pcie_gen[i] = pcie_gen_cap;
++ pcie_table->pcie_lane[i] = pcie_width_cap;
++ }
+ } else {
+- min_lane_width = MAX(1, table_member2[0]);
+- max_lane_width = MIN(pcie_width_cap, table_member2[1]);
+- min_lane_width = min_lane_width > max_lane_width ?
+- max_lane_width : min_lane_width;
++ for (i = 0; i < NUM_LINK_LEVELS; i++) {
++ if (pcie_table->pcie_gen[i] > pcie_gen_cap)
++ pcie_table->pcie_gen[i] = pcie_gen_cap;
++ if (pcie_table->pcie_lane[i] > pcie_width_cap)
++ pcie_table->pcie_lane[i] = pcie_width_cap;
++ }
+ }
+- pcie_table->pcie_lane[0] = min_lane_width;
+- pcie_table->pcie_lane[1] = max_lane_width;
+
+ for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ smu_pcie_arg = (i << 16 |
+--
+2.41.0
+
--- /dev/null
+From 072030b1783056b5de8b0fac5303a5e9dbc6cfde Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Mon, 19 Jun 2023 15:04:24 -0500
+Subject: drm/amd: Disable PSR-SU on Parade 0803 TCON
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+commit 072030b1783056b5de8b0fac5303a5e9dbc6cfde upstream.
+
+A number of users have reported that there are random hangs occurring
+caused by PSR-SU specifically on panels that contain the parade 0803
+TCON. Users have been able to work around the issue by disabling PSR
+entirely.
+
+To avoid these hangs, disable PSR-SU when this TCON is found.
+
+Cc: stable@vger.kernel.org
+Cc: Sean Wang <sean.ns.wang@amd.com>
+Cc: Marc Rossi <Marc.Rossi@amd.com>
+Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com>
+Suggested-by: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com>
+Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+@@ -816,6 +816,8 @@ bool is_psr_su_specific_panel(struct dc_
+ ((dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x08) ||
+ (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x07)))
+ isPSRSUSupported = false;
++ else if (dpcd_caps->sink_dev_id_str[1] == 0x08 && dpcd_caps->sink_dev_id_str[0] == 0x03)
++ isPSRSUSupported = false;
+ else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1)
+ isPSRSUSupported = true;
+ }
--- /dev/null
+From 0f48a4b83610cb0e4e0bc487800ab69f51b4aca6 Mon Sep 17 00:00:00 2001
+From: Sung-huai Wang <danny.wang@amd.com>
+Date: Tue, 6 Jun 2023 14:28:38 +0800
+Subject: drm/amd/display: add a NULL pointer check
+
+From: Sung-huai Wang <danny.wang@amd.com>
+
+commit 0f48a4b83610cb0e4e0bc487800ab69f51b4aca6 upstream.
+
+[Why & How]
+
+We have to check if stream is properly initialized before calling
+find_matching_pll(), otherwise we might end up trying to deferecence a
+NULL pointer.
+
+Cc: stable@vger.kernel.org # 6.1+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Sung-huai Wang <danny.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -970,10 +970,12 @@ enum dc_status resource_map_phy_clock_re
+ || dc_is_virtual_signal(pipe_ctx->stream->signal))
+ pipe_ctx->clock_source =
+ dc->res_pool->dp_clock_source;
+- else
+- pipe_ctx->clock_source = find_matching_pll(
+- &context->res_ctx, dc->res_pool,
+- stream);
++ else {
++ if (stream && stream->link && stream->link->link_enc)
++ pipe_ctx->clock_source = find_matching_pll(
++ &context->res_ctx, dc->res_pool,
++ stream);
++ }
+
+ if (pipe_ctx->clock_source == NULL)
+ return DC_NO_CLOCK_SOURCE_RESOURCE;
--- /dev/null
+From 613a7956deb3b1ffa2810c6d4c90ee9c3d743dbb Mon Sep 17 00:00:00 2001
+From: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Date: Mon, 12 Jun 2023 12:44:00 -0400
+Subject: drm/amd/display: Add monitor specific edid quirk
+
+From: Aurabindo Pillai <aurabindo.pillai@amd.com>
+
+commit 613a7956deb3b1ffa2810c6d4c90ee9c3d743dbb upstream.
+
+Disable FAMS on a Samsung Odyssey G9 monitor. Experiments show that this
+monitor does not work well under some use cases, and is likely
+implementation specific bug on the monitor's firmware.
+
+Cc: stable@vger.kernel.org
+Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
+Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 26 ++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -42,6 +42,30 @@
+ #include "dm_helpers.h"
+ #include "ddc_service_types.h"
+
++static u32 edid_extract_panel_id(struct edid *edid)
++{
++ return (u32)edid->mfg_id[0] << 24 |
++ (u32)edid->mfg_id[1] << 16 |
++ (u32)EDID_PRODUCT_ID(edid);
++}
++
++static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
++{
++ uint32_t panel_id = edid_extract_panel_id(edid);
++
++ switch (panel_id) {
++ /* Workaround for some monitors which does not work well with FAMS */
++ case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
++ case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
++ case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
++ DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
++ edid_caps->panel_patch.disable_fams = true;
++ break;
++ default:
++ return;
++ }
++}
++
+ /* dm_helpers_parse_edid_caps
+ *
+ * Parse edid caps
+@@ -113,6 +137,8 @@ enum dc_edid_status dm_helpers_parse_edi
+ else
+ edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
+
++ apply_edid_quirks(edid_buf, edid_caps);
++
+ kfree(sads);
+ kfree(sadb);
+
--- /dev/null
+From 274d205cb59f43815542e04b42a9e6d0b9b95eff Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Fri, 23 Jun 2023 10:05:19 -0500
+Subject: drm/amd/display: Correct `DMUB_FW_VERSION` macro
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+commit 274d205cb59f43815542e04b42a9e6d0b9b95eff upstream.
+
+The `DMUB_FW_VERSION` macro has a mistake in that the revision field
+is off by one byte. The last byte is typically used for other purposes
+and not a revision.
+
+Cc: stable@vger.kernel.org
+Cc: Sean Wang <sean.ns.wang@amd.com>
+Cc: Marc Rossi <Marc.Rossi@amd.com>
+Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com>
+Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+@@ -471,7 +471,7 @@ struct dmub_notification {
+ * of a firmware to know if feature or functionality is supported or present.
+ */
+ #define DMUB_FW_VERSION(major, minor, revision) \
+- ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | ((revision) & 0xFFFF))
++ ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8))
+
+ /**
+ * dmub_srv_create() - creates the DMUB service.
--- /dev/null
+From 26518b39181876064850209ecdab48c0ee5924b1 Mon Sep 17 00:00:00 2001
+From: Leo Chen <sancchen@amd.com>
+Date: Thu, 8 Jun 2023 16:37:38 -0400
+Subject: drm/amd/display: disable seamless boot if force_odm_combine is enabled
+
+From: Leo Chen <sancchen@amd.com>
+
+commit 26518b39181876064850209ecdab48c0ee5924b1 upstream.
+
+[Why & How]
+Having seamless boot on while forcing debug option ODM combine 2 to 1
+will cause some corruptions because of some missing programmings.
+
+Cc: stable@vger.kernel.org # 6.1+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Leo Chen <sancchen@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1539,6 +1539,9 @@ bool dc_validate_boot_timing(const struc
+ return false;
+ }
+
++ if (dc->debug.force_odm_combine)
++ return false;
++
+ /* Check for enabled DIG to identify enabled display */
+ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+ return false;
--- /dev/null
+From 7a0e005c7957931689a327b2a4e7333a19f13f95 Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Thu, 25 May 2023 08:37:40 -0400
+Subject: drm/amd/display: edp do not add non-edid timings
+
+From: Hersen Wu <hersenxs.wu@amd.com>
+
+commit 7a0e005c7957931689a327b2a4e7333a19f13f95 upstream.
+
+[Why] most edp support only timings from edid. applying
+non-edid timings, especially those timings out of edp
+bandwidth, may damage edp.
+
+[How] do not add non-edid timings for edp.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Acked-by: Stylon Wang <stylon.wang@amd.com>
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Roman Li <roman.li@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -6972,7 +6972,13 @@ static int amdgpu_dm_connector_get_modes
+ drm_add_modes_noedid(connector, 640, 480);
+ } else {
+ amdgpu_dm_connector_ddc_get_modes(connector, edid);
+- amdgpu_dm_connector_add_common_modes(encoder, connector);
++ /* most eDP supports only timings from its edid,
++ * usually only detailed timings are available
++ * from eDP edid. timings which are not from edid
++ * may damage eDP
++ */
++ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
++ amdgpu_dm_connector_add_common_modes(encoder, connector);
+ amdgpu_dm_connector_add_freesync_modes(connector, edid);
+ }
+ amdgpu_dm_fbc_init(connector);
--- /dev/null
+From 75c2b7ed080d7421157c03064be82275364136e7 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
+Date: Tue, 18 Apr 2023 10:11:56 -0400
+Subject: drm/amd/display: fix seamless odm transitions
+
+From: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
+
+commit 75c2b7ed080d7421157c03064be82275364136e7 upstream.
+
+Add missing programming and function pointers
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Acked-by: Stylon Wang <stylon.wang@amd.com>
+Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++++++++++
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 +
+ 3 files changed, 13 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1678,6 +1678,17 @@ static void dcn20_program_pipe(
+
+ if (hws->funcs.setup_vupdate_interrupt)
+ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
++
++ if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
++ unsigned int k1_div, k2_div;
++
++ hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
++
++ dc->res_pool->dccg->funcs->set_pixel_rate_div(
++ dc->res_pool->dccg,
++ pipe_ctx->stream_res.tg->inst,
++ k1_div, k2_div);
++ }
+ }
+
+ if (pipe_ctx->update_flags.bits.odm)
+--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+@@ -98,7 +98,7 @@ static void optc32_set_odm_combine(struc
+ optc1->opp_count = opp_cnt;
+ }
+
+-static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
++void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
+ {
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+@@ -250,5 +250,6 @@
+ SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+ void dcn32_timing_generator_init(struct optc *optc1);
++void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
+
+ #endif /* __DC_OPTC_DCN32_H__ */
--- /dev/null
+From 1966bbfdfe476d271b338336254854c5edd5a907 Mon Sep 17 00:00:00 2001
+From: Austin Zheng <austin.zheng@amd.com>
+Date: Thu, 15 Jun 2023 16:41:08 -0400
+Subject: drm/amd/display: Remove Phantom Pipe Check When Calculating K1 and K2
+
+From: Austin Zheng <austin.zheng@amd.com>
+
+commit 1966bbfdfe476d271b338336254854c5edd5a907 upstream.
+
+[Why]
+K1 and K2 not being setting properly when subVP is active.
+
+[How]
+Have phantom pipes use the same programing as the main pipes without
+checking the paired stream
+
+Cc: stable@vger.kernel.org
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
+Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
+Signed-off-by: Austin Zheng <austin.zheng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+@@ -1165,10 +1165,6 @@ unsigned int dcn32_calculate_dccg_k1_k2_
+ unsigned int odm_combine_factor = 0;
+ bool two_pix_per_container = false;
+
+- // For phantom pipes, use the same programming as the main pipes
+- if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+- stream = pipe_ctx->stream->mall_stream_config.paired_stream;
+- }
+ two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
+ odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+
--- /dev/null
+From 8a774fe912ff09e39c2d3a3589c729330113f388 Mon Sep 17 00:00:00 2001
+From: gaba <gaba@amd.com>
+Date: Thu, 2 Mar 2023 19:03:56 -0500
+Subject: drm/amdgpu: avoid restore process run into dead loop.
+
+From: gaba <gaba@amd.com>
+
+commit 8a774fe912ff09e39c2d3a3589c729330113f388 upstream.
+
+In restore process worker, pinned BO cause update PTE fail, then
+the function re-schedule the restore_work. This will generate dead loop.
+
+Signed-off-by: gaba <gaba@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -2737,6 +2737,9 @@ int amdgpu_amdkfd_gpuvm_restore_process_
+ if (!attachment->is_mapped)
+ continue;
+
++ if (attachment->bo_va->base.bo->tbo.pin_count)
++ continue;
++
+ kfd_mem_dmaunmap_attachment(mem, attachment);
+ ret = update_gpuvm_pte(mem, attachment, &sync_obj);
+ if (ret) {
--- /dev/null
+From ea2c3c08554601b051d91403a241266e1cf490a5 Mon Sep 17 00:00:00 2001
+From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
+Date: Fri, 16 Jun 2023 15:14:07 +0200
+Subject: drm/amdgpu: fix clearing mappings for BOs that are always valid in VM
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
+
+commit ea2c3c08554601b051d91403a241266e1cf490a5 upstream.
+
+Per VM BOs must be marked as moved or otherwise their ranges are not
+updated on use which might be necessary when the replace operation
+splits mappings.
+
+This fixes random GPU hangs when replacing sparse mappings from the
+userspace, while OP_MAP/OP_UNMAP works fine because always valid BOs
+are correctly handled there.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1668,18 +1668,30 @@ int amdgpu_vm_bo_clear_mappings(struct a
+
+ /* Insert partial mapping before the range */
+ if (!list_empty(&before->list)) {
++ struct amdgpu_bo *bo = before->bo_va->base.bo;
++
+ amdgpu_vm_it_insert(before, &vm->va);
+ if (before->flags & AMDGPU_PTE_PRT)
+ amdgpu_vm_prt_get(adev);
++
++ if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
++ !before->bo_va->base.moved)
++ amdgpu_vm_bo_moved(&before->bo_va->base);
+ } else {
+ kfree(before);
+ }
+
+ /* Insert partial mapping after the range */
+ if (!list_empty(&after->list)) {
++ struct amdgpu_bo *bo = after->bo_va->base.bo;
++
+ amdgpu_vm_it_insert(after, &vm->va);
+ if (after->flags & AMDGPU_PTE_PRT)
+ amdgpu_vm_prt_get(adev);
++
++ if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
++ !after->bo_va->base.moved)
++ amdgpu_vm_bo_moved(&after->bo_va->base);
+ } else {
+ kfree(after);
+ }
--- /dev/null
+From a590f03d8de7c4cb7ce4916dc7f2fd10711faabe Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= <thomas.hellstrom@linux.intel.com>
+Date: Mon, 26 Jun 2023 11:14:50 +0200
+Subject: drm/ttm: Don't leak a resource on swapout move error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
+
+commit a590f03d8de7c4cb7ce4916dc7f2fd10711faabe upstream.
+
+If moving the bo to system for swapout failed, we were leaking
+a resource. Fix.
+
+Fixes: bfa3357ef9ab ("drm/ttm: allocate resource object instead of embedding it v2")
+Cc: Christian König <christian.koenig@amd.com>
+Cc: "Christian König" <ckoenig.leichtzumerken@gmail.com>
+Cc: dri-devel@lists.freedesktop.org
+Cc: <stable@vger.kernel.org> # v5.14+
+Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
+Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
+Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20230626091450.14757-5-thomas.hellstrom@linux.intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/ttm/ttm_bo.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/ttm/ttm_bo.c
++++ b/drivers/gpu/drm/ttm/ttm_bo.c
+@@ -1165,6 +1165,7 @@ int ttm_bo_swapout(struct ttm_buffer_obj
+ ret = ttm_bo_handle_move_mem(bo, evict_mem, true, &ctx, &hop);
+ if (unlikely(ret != 0)) {
+ WARN(ret == -EMULTIHOP, "Unexpected multihop in swaput - likely driver bug.\n");
++ ttm_resource_free(bo, &evict_mem);
+ goto out;
+ }
+ }
--- /dev/null
+From 4481913607e58196c48a4fef5e6f45350684ec3c Mon Sep 17 00:00:00 2001
+From: Yunxiang Li <Yunxiang.Li@amd.com>
+Date: Thu, 22 Jun 2023 10:18:03 -0400
+Subject: drm/ttm: fix bulk_move corruption when adding a entry
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Yunxiang Li <Yunxiang.Li@amd.com>
+
+commit 4481913607e58196c48a4fef5e6f45350684ec3c upstream.
+
+When the resource is the first in the bulk_move range, adding it again
+(thus moving it to the tail) will corrupt the list since the first
+pointer is not moved. This eventually lead to null pointer deref in
+ttm_lru_bulk_move_del()
+
+Fixes: fee2ede15542 ("drm/ttm: rework bulk move handling v5")
+Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+CC: stable@vger.kernel.org
+Link: https://patchwork.freedesktop.org/patch/msgid/20230622141902.28718-3-Yunxiang.Li@amd.com
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/ttm/ttm_resource.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/ttm/ttm_resource.c
++++ b/drivers/gpu/drm/ttm/ttm_resource.c
+@@ -85,6 +85,8 @@ static void ttm_lru_bulk_move_pos_tail(s
+ struct ttm_resource *res)
+ {
+ if (pos->last != res) {
++ if (pos->first == res)
++ pos->first = list_next_entry(res, lru);
+ list_move(&res->lru, &pos->last->lru);
+ pos->last = res;
+ }
+@@ -110,7 +112,8 @@ static void ttm_lru_bulk_move_del(struct
+ {
+ struct ttm_lru_bulk_move_pos *pos = ttm_lru_bulk_move_pos(bulk, res);
+
+- if (unlikely(pos->first == res && pos->last == res)) {
++ if (unlikely(WARN_ON(!pos->first || !pos->last) ||
++ pos->first == res && pos->last == res)) {
+ pos->first = NULL;
+ pos->last = NULL;
+ } else if (pos->first == res) {
--- /dev/null
+From a2848d08742c8e8494675892c02c0d22acbe3cf8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 7 Jul 2023 11:25:00 +0200
+Subject: drm/ttm: never consider pinned BOs for eviction&swap
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Christian König <christian.koenig@amd.com>
+
+commit a2848d08742c8e8494675892c02c0d22acbe3cf8 upstream.
+
+There is a small window where we have already incremented the pin count
+but not yet moved the bo from the lru to the pinned list.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reported-by: Pelloux-Prayer, Pierre-Eric <Pierre-eric.Pelloux-prayer@amd.com>
+Tested-by: Pelloux-Prayer, Pierre-Eric <Pierre-eric.Pelloux-prayer@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Link: https://patchwork.freedesktop.org/patch/msgid/20230707120826.3701-1-christian.koenig@amd.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/ttm/ttm_bo.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/gpu/drm/ttm/ttm_bo.c
++++ b/drivers/gpu/drm/ttm/ttm_bo.c
+@@ -549,6 +549,12 @@ static bool ttm_bo_evict_swapout_allowab
+ {
+ bool ret = false;
+
++ if (bo->pin_count) {
++ *locked = false;
++ *busy = false;
++ return false;
++ }
++
+ if (bo->base.resv == ctx->resv) {
+ dma_resv_assert_held(bo->base.resv);
+ if (ctx->allow_res_evict)
--- /dev/null
+From 1995f15590ca222f91193ed11461862b450abfd6 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Tue, 13 Jun 2023 16:15:21 -0500
+Subject: firmware: stratix10-svc: Fix a potential resource leak in svc_create_memory_pool()
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+commit 1995f15590ca222f91193ed11461862b450abfd6 upstream.
+
+svc_create_memory_pool() is only called from stratix10_svc_drv_probe().
+Most of resources in the probe are managed, but not this memremap() call.
+
+There is also no memunmap() call in the file.
+
+So switch to devm_memremap() to avoid a resource leak.
+
+Cc: stable@vger.kernel.org
+Fixes: 7ca5ce896524 ("firmware: add Intel Stratix10 service layer driver")
+Link: https://lore.kernel.org/all/783e9dfbba34e28505c9efa8bba41f97fd0fa1dc.1686109400.git.christophe.jaillet@wanadoo.fr/
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
+Message-ID: <20230613211521.16366-1-dinguyen@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/firmware/stratix10-svc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/firmware/stratix10-svc.c
++++ b/drivers/firmware/stratix10-svc.c
+@@ -755,7 +755,7 @@ svc_create_memory_pool(struct platform_d
+ end = rounddown(sh_memory->addr + sh_memory->size, PAGE_SIZE);
+ paddr = begin;
+ size = end - begin;
+- va = memremap(paddr, size, MEMREMAP_WC);
++ va = devm_memremap(dev, paddr, size, MEMREMAP_WC);
+ if (!va) {
+ dev_err(dev, "fail to remap shared memory\n");
+ return ERR_PTR(-EINVAL);
--- /dev/null
+From 27a826837ec9a3e94cc44bd9328b8289b0fcecd7 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@linaro.org>
+Date: Mon, 19 Jun 2023 12:45:17 +0300
+Subject: serial: atmel: don't enable IRQs prematurely
+
+From: Dan Carpenter <dan.carpenter@linaro.org>
+
+commit 27a826837ec9a3e94cc44bd9328b8289b0fcecd7 upstream.
+
+The atmel_complete_tx_dma() function disables IRQs at the start
+of the function by calling spin_lock_irqsave(&port->lock, flags);
+There is no need to disable them a second time using the
+spin_lock_irq() function and, in fact, doing so is a bug because
+it will enable IRQs prematurely when we call spin_unlock_irq().
+
+Just use spin_lock/unlock() instead without disabling or enabling
+IRQs.
+
+Fixes: 08f738be88bb ("serial: at91: add tx dma support")
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
+Acked-by: Richard Genoud <richard.genoud@gmail.com>
+Link: https://lore.kernel.org/r/cb7c39a9-c004-4673-92e1-be4e34b85368@moroto.mountain
+Cc: stable <stable@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/atmel_serial.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/tty/serial/atmel_serial.c
++++ b/drivers/tty/serial/atmel_serial.c
+@@ -880,11 +880,11 @@ static void atmel_complete_tx_dma(void *
+
+ port->icount.tx += atmel_port->tx_len;
+
+- spin_lock_irq(&atmel_port->lock_tx);
++ spin_lock(&atmel_port->lock_tx);
+ async_tx_ack(atmel_port->desc_tx);
+ atmel_port->cookie_tx = -EINVAL;
+ atmel_port->desc_tx = NULL;
+- spin_unlock_irq(&atmel_port->lock_tx);
++ spin_unlock(&atmel_port->lock_tx);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
scsi-lpfc-fix-double-free-in-lpfc_cmpl_els_logo_acc-caused-by-lpfc_nlp_not_used.patch
drm-atomic-allow-vblank-enabled-self-refresh-disable.patch
drm-rockchip-vop-leave-vblank-enabled-in-self-refresh.patch
+drm-amd-display-fix-seamless-odm-transitions.patch
+drm-amd-display-edp-do-not-add-non-edid-timings.patch
+drm-amd-display-remove-phantom-pipe-check-when-calculating-k1-and-k2.patch
+drm-amd-display-disable-seamless-boot-if-force_odm_combine-is-enabled.patch
+drm-amdgpu-fix-clearing-mappings-for-bos-that-are-always-valid-in-vm.patch
+drm-amd-disable-psr-su-on-parade-0803-tcon.patch
+drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch
+drm-amd-display-add-a-null-pointer-check.patch
+drm-amd-display-correct-dmub_fw_version-macro.patch
+drm-amd-display-add-monitor-specific-edid-quirk.patch
+drm-amdgpu-avoid-restore-process-run-into-dead-loop.patch
+drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch
+drm-ttm-don-t-leak-a-resource-on-swapout-move-error.patch
+drm-ttm-never-consider-pinned-bos-for-eviction-swap.patch
+serial-atmel-don-t-enable-irqs-prematurely.patch
+tty-serial-samsung_tty-fix-a-memory-leak-in-s3c24xx_serial_getclk-in-case-of-error.patch
+tty-serial-samsung_tty-fix-a-memory-leak-in-s3c24xx_serial_getclk-when-iterating-clk.patch
+tty-serial-imx-fix-rs485-rx-after-tx.patch
+firmware-stratix10-svc-fix-a-potential-resource-leak-in-svc_create_memory_pool.patch
--- /dev/null
+From 639949a7031e04c59ec91614eceb9543e9120f43 Mon Sep 17 00:00:00 2001
+From: Martin Fuzzey <martin.fuzzey@flowbird.group>
+Date: Fri, 16 Jun 2023 12:47:23 +0200
+Subject: tty: serial: imx: fix rs485 rx after tx
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Martin Fuzzey <martin.fuzzey@flowbird.group>
+
+commit 639949a7031e04c59ec91614eceb9543e9120f43 upstream.
+
+Since commit 79d0224f6bf2 ("tty: serial: imx: Handle RS485 DE signal
+active high") RS485 reception no longer works after a transmission.
+
+The following scenario shows the problem:
+ 1) Open a port in RS485 mode
+ 2) Receive data from remote (OK)
+ 3) Transmit data to remote (OK)
+ 4) Receive data from remote (Nothing received)
+
+In RS485 mode, imx_uart_start_tx() calls imx_uart_stop_rx() and, when the
+transmission is complete, imx_uart_stop_tx() calls imx_uart_start_rx().
+
+Since the above commit imx_uart_stop_rx() now sets the loopback bit but
+imx_uart_start_rx() does not clear it causing the hardware to remain in
+loopback mode and not receive external data.
+
+Fix this by moving the existing loopback disable code to a helper function
+and calling it from imx_uart_start_rx() too.
+
+Fixes: 79d0224f6bf2 ("tty: serial: imx: Handle RS485 DE signal active high")
+Cc: stable@vger.kernel.org
+Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
+Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+Link: https://lore.kernel.org/r/20230616104838.2729694-1-martin.fuzzey@flowbird.group
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/imx.c | 18 +++++++++++++-----
+ 1 file changed, 13 insertions(+), 5 deletions(-)
+
+--- a/drivers/tty/serial/imx.c
++++ b/drivers/tty/serial/imx.c
+@@ -397,6 +397,16 @@ static void start_hrtimer_ms(struct hrti
+ hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
+ }
+
++static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
++{
++ unsigned int uts;
++
++ /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
++ uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
++ uts &= ~UTS_LOOP;
++ imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
++}
++
+ /* called with port.lock taken and irqs off */
+ static void imx_uart_start_rx(struct uart_port *port)
+ {
+@@ -418,6 +428,7 @@ static void imx_uart_start_rx(struct uar
+ /* Write UCR2 first as it includes RXEN */
+ imx_uart_writel(sport, ucr2, UCR2);
+ imx_uart_writel(sport, ucr1, UCR1);
++ imx_uart_disable_loopback_rs485(sport);
+ }
+
+ /* called with port.lock taken and irqs off */
+@@ -1404,7 +1415,7 @@ static int imx_uart_startup(struct uart_
+ int retval, i;
+ unsigned long flags;
+ int dma_is_inited = 0;
+- u32 ucr1, ucr2, ucr3, ucr4, uts;
++ u32 ucr1, ucr2, ucr3, ucr4;
+
+ retval = clk_prepare_enable(sport->clk_per);
+ if (retval)
+@@ -1509,10 +1520,7 @@ static int imx_uart_startup(struct uart_
+ imx_uart_writel(sport, ucr2, UCR2);
+ }
+
+- /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
+- uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
+- uts &= ~UTS_LOOP;
+- imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
++ imx_uart_disable_loopback_rs485(sport);
+
+ spin_unlock_irqrestore(&sport->port.lock, flags);
+
--- /dev/null
+From a9c09546e903f1068acfa38e1ee18bded7114b37 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sat, 10 Jun 2023 17:59:25 +0200
+Subject: tty: serial: samsung_tty: Fix a memory leak in s3c24xx_serial_getclk() in case of error
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+commit a9c09546e903f1068acfa38e1ee18bded7114b37 upstream.
+
+If clk_get_rate() fails, the clk that has just been allocated needs to be
+freed.
+
+Cc: <stable@vger.kernel.org> # v3.3+
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
+Fixes: 5f5a7a5578c5 ("serial: samsung: switch to clkdev based clock lookup")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
+Message-ID: <e4baf6039368f52e5a5453982ddcb9a330fc689e.1686412569.git.christophe.jaillet@wanadoo.fr>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/samsung_tty.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/samsung_tty.c
++++ b/drivers/tty/serial/samsung_tty.c
+@@ -1467,8 +1467,12 @@ static unsigned int s3c24xx_serial_getcl
+ continue;
+
+ rate = clk_get_rate(clk);
+- if (!rate)
++ if (!rate) {
++ dev_err(ourport->port.dev,
++ "Failed to get clock rate for %s.\n", clkname);
++ clk_put(clk);
+ continue;
++ }
+
+ if (ourport->info->has_divslot) {
+ unsigned long div = rate / req_baud;
--- /dev/null
+From 832e231cff476102e8204a9e7bddfe5c6154a375 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sat, 10 Jun 2023 17:59:26 +0200
+Subject: tty: serial: samsung_tty: Fix a memory leak in s3c24xx_serial_getclk() when iterating clk
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+commit 832e231cff476102e8204a9e7bddfe5c6154a375 upstream.
+
+When the best clk is searched, we iterate over all possible clk.
+
+If we find a better match, the previous one, if any, needs to be freed.
+If a better match has already been found, we still need to free the new
+one, otherwise it leaks.
+
+Cc: <stable@vger.kernel.org> # v3.3+
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
+Fixes: 5f5a7a5578c5 ("serial: samsung: switch to clkdev based clock lookup")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
+Message-ID: <cf3e0053d2fc7391b2d906a86cd01a5ef15fb9dc.1686412569.git.christophe.jaillet@wanadoo.fr>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/samsung_tty.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/tty/serial/samsung_tty.c
++++ b/drivers/tty/serial/samsung_tty.c
+@@ -1498,10 +1498,18 @@ static unsigned int s3c24xx_serial_getcl
+ calc_deviation = -calc_deviation;
+
+ if (calc_deviation < deviation) {
++ /*
++ * If we find a better clk, release the previous one, if
++ * any.
++ */
++ if (!IS_ERR(*best_clk))
++ clk_put(*best_clk);
+ *best_clk = clk;
+ best_quot = quot;
+ *clk_num = cnt;
+ deviation = calc_deviation;
++ } else {
++ clk_put(clk);
+ }
+ }
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
