versal-vc-p-a2197-00-revA.dtb \
versal-vc-p-a2197-00-revA-x-prc-01-revA.dtb \
versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi.dtb \
- versal-vc-p-a2197-00-revA-x-prc-02-revA.dtb
+ versal-vc-p-a2197-00-revA-x-prc-02-revA.dtb \
+ versal-vc-d-d1760-01-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "versal.dtsi"
+#include "versal-fixed.dtsi"
+
+/ {
+ compatible = "xlnx,versal-vc-d-d1760-01-revA",
+ "xlnx,versal-vc-d-d1760-01",
+ "xlnx,versal-vc-d-d1760", "xlnx,versal";
+ model = "Xilinx Versal d1760 Processor board revA"; /* xbb2525/v350 */
+
+ chosen {
+ bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused";
+ stdout-path = "serial0:115200";
+ };
+
+ aliases {
+ serial0 = &serial1;
+ serial1 = &serial0;
+ };
+
+ memory: memory@0 {
+ device_type = "memory"; /* 16GB total via MC0/1/2/3 */
+ reg = <0 0 0 0x80000000>; /* 2GB here */
+ /* <0x8 0x0 0x3 0x80000000> */ /* 12GB - enable it later */
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&serial0 {
+ status = "disabled"; /* communication with MSP432 */
+};
+
+&serial1 {
+ status = "okay";
+};
# CONFIG_PARTITION_UUIDS is not set
CONFIG_OF_BOARD=y
CONFIG_DEFAULT_DEVICE_TREE="versal-vc-p-a2197-00-revA-x-prc-01-revA"
-CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA"
+CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA versal-vc-d-d1760-01-revA"
CONFIG_MULTI_DTB_FIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y