drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registers

Convert the gen9+ timestamo frequency related registers to
the modern REG_BIT()/etc. style.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-12-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 6e63505fe47818223ac4b5b56fa1c999c08f2ab0..6c499692d61ef36f67a5ec67fd5e315e0eb42619 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -35,9 +35,7 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
        u32 f24_mhz = 24000000;
        u32 f25_mhz = 25000000;
        u32 f38_4_mhz = 38400000;
-       u32 crystal_clock =
-               (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
-               GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+       u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
 
        switch (crystal_clock) {
        case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
@@ -80,8 +78,7 @@ static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
                 * register increments from this frequency (it might
                 * increment only every few clock cycle).
                 */
-               freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
-                             GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+               freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
        }
 
        return freq;
@@ -102,8 +99,7 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
                 * register increments from this frequency (it might
                 * increment only every few clock cycle).
                 */
-               freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
-                             CTC_SHIFT_PARAMETER_SHIFT);
+               freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg);
        }
 
        return freq;

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f147c36f35a9bc869845df1a06498f748eea59a6..bbb2e14261467b28bcd3685359974b730b62777b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -30,18 +30,15 @@
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0                            _MMIO(0xd00)
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT    3
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK     (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
-#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ   1
-#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT   3
-#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK    (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ  0
-#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ        1
-#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ        2
-#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ  3
-#define   GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT  1
-#define   GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK   (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
+#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK     REG_BIT(3)
+#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
+#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ   REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
+#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK    REG_GENMASK(5, 3)
+#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ  REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
+#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ        REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
+#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ        REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
+#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ  REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
+#define   GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK   REG_GENMASK(2, 1)
 
 #define RPM_CONFIG1                            _MMIO(0xd04)
 #define   GEN10_GT_NOA_ENABLE                  (1 << 9)
@@ -882,11 +879,10 @@
 
 /* GPM unit config (Gen9+) */
 #define CTC_MODE                               _MMIO(0xa26c)
-#define   CTC_SOURCE_PARAMETER_MASK            1
-#define   CTC_SOURCE_CRYSTAL_CLOCK             0
-#define   CTC_SOURCE_DIVIDE_LOGIC              1
-#define   CTC_SHIFT_PARAMETER_SHIFT            1
-#define   CTC_SHIFT_PARAMETER_MASK             (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
+#define   CTC_SOURCE_PARAMETER_MASK            REG_BIT(0)
+#define   CTC_SOURCE_CRYSTAL_CLOCK             REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0)
+#define   CTC_SOURCE_DIVIDE_LOGIC              REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1)
+#define   CTC_SHIFT_PARAMETER_MASK             REG_GENMASK(2, 1)
 
 /* GPM MSG_IDLE */
 #define MSG_IDLE_CS            _MMIO(0x8000)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3fce5c00014448b79183f19bfeec91a8bf08167d..30ec92f1b2a46a4d6f989124ab978a5165b8c337 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1285,15 +1285,12 @@ static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
 static u32 gpm_timestamp_shift(struct intel_gt *gt)
 {
        intel_wakeref_t wakeref;
-       u32 reg, shift;
+       u32 reg;
 
        with_intel_runtime_pm(gt->uncore->rpm, wakeref)
                reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
 
-       shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
-               GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
-
-       return 3 - shift;
+       return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
 }
 
 static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)