intel_dsc_enable(pipe_crtc_state);
- if (DISPLAY_VER(dev_priv) >= 13)
+ if (HAS_UNCOMPRESSED_JOINER(dev_priv))
intel_uncompressed_joiner_enable(pipe_crtc_state);
intel_set_pipe_src_size(pipe_crtc_state);
*primary_pipes = 0;
*secondary_pipes = 0;
+ if (!HAS_BIGJOINER(dev_priv))
+ return;
+
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
joiner_pipes(dev_priv)) {
enum intel_display_power_domain power_domain;
*secondary_pipes |= BIT(pipe);
}
- if (DISPLAY_VER(dev_priv) < 13)
+ if (!HAS_UNCOMPRESSED_JOINER(dev_priv))
continue;
power_domain = POWER_DOMAIN_PIPE(pipe);
int max_dotclock = i915->display.cdclk.max_dotclk_freq;
/* icl+ might use joiner */
- if (DISPLAY_VER(i915) >= 11)
+ if (HAS_BIGJOINER(i915))
max_dotclock *= 2;
return max_dotclock;
connector, &i915_dsc_fractional_bpp_fops);
}
- if (DISPLAY_VER(i915) >= 11 &&
+ if (HAS_BIGJOINER(i915) &&
(connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_eDP)) {
debugfs_create_bool("i915_bigjoiner_force_enable", 0644, root,
#define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
+#define HAS_BIGJOINER(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))
#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
+#define HAS_UNCOMPRESSED_JOINER(i915) (DISPLAY_VER(i915) >= 13)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
* limitation. DG2 onwards pipe joiner can be enabled without
* compression.
*/
- return DISPLAY_VER(i915) < 13 && use_joiner;
+ return !HAS_UNCOMPRESSED_JOINER(i915) && use_joiner;
}
static int