arm64: dts: qcom: x1e80100: fix PCIe4 and PCIe6a PHY clocks

Add the missing clkref enable and pipediv2 clocks to the PCIe4 and
PCIe6a PHYs.

Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Cc: stable@vger.kernel.org	# 6.9
Cc: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240916082307.29393-3-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a36076e3c56b5b8815eb41ec55e2e1e5bd878201..6a91c46ee687c642b7e77fcb21ecb34c91e588fe 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3002,14 +3002,16 @@
 
                        clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
-                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
                                 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
-                                <&gcc GCC_PCIE_6A_PIPE_CLK>;
+                                <&gcc GCC_PCIE_6A_PIPE_CLK>,
+                                <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
                        clock-names = "aux",
                                      "cfg_ahb",
                                      "ref",
                                      "rchng",
-                                     "pipe";
+                                     "pipe",
+                                     "pipediv2";
 
                        resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
                                 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
@@ -3254,14 +3256,16 @@
 
                        clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
                                 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
-                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,
                                 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
-                                <&gcc GCC_PCIE_4_PIPE_CLK>;
+                                <&gcc GCC_PCIE_4_PIPE_CLK>,
+                                <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
                        clock-names = "aux",
                                      "cfg_ahb",
                                      "ref",
                                      "rchng",
-                                     "pipe";
+                                     "pipe",
+                                     "pipediv2";
 
                        resets = <&gcc GCC_PCIE_4_PHY_BCR>;
                        reset-names = "phy";