morello: Fix encoding of ldtr/sttr

This patch fixes the encoding of the immediate in the A64C ldtr/sttr
instructions. Prior to this patch, GAS would accept immediates for these
instructions that were not multiples of 16, and would not scale the
immediate by 16.

gas/ChangeLog:

2021-09-24  Alex Coplan  <alex.coplan@arm.com>

	* testsuite/gas/aarch64/morello_ldst-c64.d: Update following
	test + encoding change.
	* testsuite/gas/aarch64/morello_ldst-invalid.d: New test.
	* testsuite/gas/aarch64/morello_ldst-invalid.l: New test.
	* testsuite/gas/aarch64/morello_ldst-invalid.s: New test.
	* testsuite/gas/aarch64/morello_ldst.d: Update following
	test + encoding change.
	* testsuite/gas/aarch64/morello_ldst.s: Update to use valid
	immediates for ldtr/sttr instructions.

opcodes/ChangeLog:

2021-09-24  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Update A64C_INSNs
	ldtr/sttr to take A64C_ADDR_SIMM9 instead of ADDR_SIMM9
	operands.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 06ff1d04022dcc6f4027e2f09d7ff18aee9cf78a..56ff44ce127d9583a98bdfc7916d23837022854b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2021-09-24  Alex Coplan  <alex.coplan@arm.com>
+
+       * testsuite/gas/aarch64/morello_ldst-c64.d: Update following
+       test + encoding change.
+       * testsuite/gas/aarch64/morello_ldst-invalid.d: New test.
+       * testsuite/gas/aarch64/morello_ldst-invalid.l: New test.
+       * testsuite/gas/aarch64/morello_ldst-invalid.s: New test.
+       * testsuite/gas/aarch64/morello_ldst.d: Update following
+       test + encoding change.
+       * testsuite/gas/aarch64/morello_ldst.s: Update to use valid
+       immediates for ldtr/sttr instructions.
+
 2021-07-29  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * config/tc-aarch64.c (aarch64_abi_type): Introduce PURECAP and HYBRID

diff --git a/gas/testsuite/gas/aarch64/morello_ldst-c64.d b/gas/testsuite/gas/aarch64/morello_ldst-c64.d
index e5df227b07d3e62fdc414fd8a5df81beb75dc789..5165b77b3382b7223aea7745c8aa2d9fee3b1d15 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst-c64.d
+++ b/gas/testsuite/gas/aarch64/morello_ldst-c64.d
@@ -66,34 +66,34 @@ Disassembly of section \.text:
 .*:    a2501304        ldur    c4, \[c24, #-255\]
 .*:    a2400304        ldur    c4, \[c24\]
 .*:    a2410304        ldur    c4, \[c24, #16\]
-.*:    a24ffb04        ldtr    c4, \[c24, #255\]
-.*:    a2501b04        ldtr    c4, \[c24, #-255\]
-.*:    a2400b04        ldtr    c4, \[c24\]
-.*:    a2410b04        ldtr    c4, \[c24, #16\]
 .*:    a20ff304        stur    c4, \[c24, #255\]
 .*:    a2101304        stur    c4, \[c24, #-255\]
 .*:    a2000304        stur    c4, \[c24\]
 .*:    a2010304        stur    c4, \[c24, #16\]
-.*:    a20ffb04        sttr    c4, \[c24, #255\]
-.*:    a2101b04        sttr    c4, \[c24, #-255\]
-.*:    a2000b04        sttr    c4, \[c24\]
-.*:    a2010b04        sttr    c4, \[c24, #16\]
 .*:    a24ff3e4        ldur    c4, \[csp, #255\]
 .*:    a25013e4        ldur    c4, \[csp, #-255\]
 .*:    a24003e4        ldur    c4, \[csp\]
 .*:    a24103e4        ldur    c4, \[csp, #16\]
-.*:    a24ffbe4        ldtr    c4, \[csp, #255\]
-.*:    a2501be4        ldtr    c4, \[csp, #-255\]
-.*:    a2400be4        ldtr    c4, \[csp\]
-.*:    a2410be4        ldtr    c4, \[csp, #16\]
 .*:    a20ff3e4        stur    c4, \[csp, #255\]
 .*:    a21013e4        stur    c4, \[csp, #-255\]
 .*:    a20003e4        stur    c4, \[csp\]
 .*:    a20103e4        stur    c4, \[csp, #16\]
-.*:    a20ffbe4        sttr    c4, \[csp, #255\]
-.*:    a2101be4        sttr    c4, \[csp, #-255\]
+.*:    a24ffb04        ldtr    c4, \[c24, #4080\]
+.*:    a2500b04        ldtr    c4, \[c24, #-4096\]
+.*:    a2400b04        ldtr    c4, \[c24\]
+.*:    a2401b04        ldtr    c4, \[c24, #16\]
+.*:    a20ffb04        sttr    c4, \[c24, #4080\]
+.*:    a2100b04        sttr    c4, \[c24, #-4096\]
+.*:    a2000b04        sttr    c4, \[c24\]
+.*:    a2001b04        sttr    c4, \[c24, #16\]
+.*:    a24ffbe4        ldtr    c4, \[csp, #4080\]
+.*:    a2500be4        ldtr    c4, \[csp, #-4096\]
+.*:    a2400be4        ldtr    c4, \[csp\]
+.*:    a2401be4        ldtr    c4, \[csp, #16\]
+.*:    a20ffbe4        sttr    c4, \[csp, #4080\]
+.*:    a2100be4        sttr    c4, \[csp, #-4096\]
 .*:    a2000be4        sttr    c4, \[csp\]
-.*:    a2010be4        sttr    c4, \[csp, #16\]
+.*:    a2001be4        sttr    c4, \[csp, #16\]
 .*:    42df9704        ldp     c4, c5, \[c24, #1008\]
 .*:    42e01704        ldp     c4, c5, \[c24, #-1024\]
 .*:    42c09704        ldp     c4, c5, \[c24, #16\]

diff --git a/gas/testsuite/gas/aarch64/morello_ldst-invalid.d b/gas/testsuite/gas/aarch64/morello_ldst-invalid.d
new file mode 100644 (file)
index 0000000..8346327
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/morello_ldst-invalid.d
@@ -0,0 +1,4 @@
+#name: Invalid Morello loads/stores
+#as: -march=morello
+#source: morello_ldst-invalid.s
+#error_output: morello_ldst-invalid.l

diff --git a/gas/testsuite/gas/aarch64/morello_ldst-invalid.l b/gas/testsuite/gas/aarch64/morello_ldst-invalid.l
new file mode 100644 (file)
index 0000000..ff4d525
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/morello_ldst-invalid.l
@@ -0,0 +1,13 @@
+[^:]*: Assembler messages:
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#1\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#2\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#7\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#4079\]'
+.*: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldtr c0,\[x1,#4081\]'
+.*: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldtr c0,\[x1,#4096\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#-1\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#-2\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#-7\]'
+.*: Error: immediate value must be a multiple of 16 at operand 2 -- `ldtr c0,\[x1,#-4095\]'
+.*: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldtr c0,\[x1,#-4097\]'
+.*: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldtr c0,\[x1,#-4112\]'

diff --git a/gas/testsuite/gas/aarch64/morello_ldst-invalid.s b/gas/testsuite/gas/aarch64/morello_ldst-invalid.s
new file mode 100644 (file)
index 0000000..4a7eacc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/morello_ldst-invalid.s
@@ -0,0 +1,12 @@
+ldtr c0, [x1, #1]
+ldtr c0, [x1, #2]
+ldtr c0, [x1, #7]
+ldtr c0, [x1, #4079]
+ldtr c0, [x1, #4081]
+ldtr c0, [x1, #4096]
+ldtr c0, [x1, #-1]
+ldtr c0, [x1, #-2]
+ldtr c0, [x1, #-7]
+ldtr c0, [x1, #-4095]
+ldtr c0, [x1, #-4097]
+ldtr c0, [x1, #-4112]

diff --git a/gas/testsuite/gas/aarch64/morello_ldst.d b/gas/testsuite/gas/aarch64/morello_ldst.d
index 0ffc967661c1b587b1b058eeec019bc8a4b2a4c4..e09d7b730d706e9362ab1558842492eb9f065063 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst.d
+++ b/gas/testsuite/gas/aarch64/morello_ldst.d
@@ -65,34 +65,34 @@ Disassembly of section \.text:
 .*:    a2501164        ldur    c4, \[x11, #-255\]
 .*:    a2400164        ldur    c4, \[x11\]
 .*:    a2410164        ldur    c4, \[x11, #16\]
-.*:    a24ff964        ldtr    c4, \[x11, #255\]
-.*:    a2501964        ldtr    c4, \[x11, #-255\]
-.*:    a2400964        ldtr    c4, \[x11\]
-.*:    a2410964        ldtr    c4, \[x11, #16\]
 .*:    a20ff164        stur    c4, \[x11, #255\]
 .*:    a2101164        stur    c4, \[x11, #-255\]
 .*:    a2000164        stur    c4, \[x11\]
 .*:    a2010164        stur    c4, \[x11, #16\]
-.*:    a20ff964        sttr    c4, \[x11, #255\]
-.*:    a2101964        sttr    c4, \[x11, #-255\]
-.*:    a2000964        sttr    c4, \[x11\]
-.*:    a2010964        sttr    c4, \[x11, #16\]
 .*:    a24ff3e4        ldur    c4, \[sp, #255\]
 .*:    a25013e4        ldur    c4, \[sp, #-255\]
 .*:    a24003e4        ldur    c4, \[sp\]
 .*:    a24103e4        ldur    c4, \[sp, #16\]
-.*:    a24ffbe4        ldtr    c4, \[sp, #255\]
-.*:    a2501be4        ldtr    c4, \[sp, #-255\]
-.*:    a2400be4        ldtr    c4, \[sp\]
-.*:    a2410be4        ldtr    c4, \[sp, #16\]
 .*:    a20ff3e4        stur    c4, \[sp, #255\]
 .*:    a21013e4        stur    c4, \[sp, #-255\]
 .*:    a20003e4        stur    c4, \[sp\]
 .*:    a20103e4        stur    c4, \[sp, #16\]
-.*:    a20ffbe4        sttr    c4, \[sp, #255\]
-.*:    a2101be4        sttr    c4, \[sp, #-255\]
+.*:    a24ff964        ldtr    c4, \[x11, #4080\]
+.*:    a2500964        ldtr    c4, \[x11, #-4096\]
+.*:    a2400964        ldtr    c4, \[x11\]
+.*:    a2401964        ldtr    c4, \[x11, #16\]
+.*:    a20ff964        sttr    c4, \[x11, #4080\]
+.*:    a2100964        sttr    c4, \[x11, #-4096\]
+.*:    a2000964        sttr    c4, \[x11\]
+.*:    a2001964        sttr    c4, \[x11, #16\]
+.*:    a24ffbe4        ldtr    c4, \[sp, #4080\]
+.*:    a2500be4        ldtr    c4, \[sp, #-4096\]
+.*:    a2400be4        ldtr    c4, \[sp\]
+.*:    a2401be4        ldtr    c4, \[sp, #16\]
+.*:    a20ffbe4        sttr    c4, \[sp, #4080\]
+.*:    a2100be4        sttr    c4, \[sp, #-4096\]
 .*:    a2000be4        sttr    c4, \[sp\]
-.*:    a2010be4        sttr    c4, \[sp, #16\]
+.*:    a2001be4        sttr    c4, \[sp, #16\]
 .*:    42df9564        ldp     c4, c5, \[x11, #1008\]
 .*:    42e01564        ldp     c4, c5, \[x11, #-1024\]
 .*:    42c09564        ldp     c4, c5, \[x11, #16\]

diff --git a/gas/testsuite/gas/aarch64/morello_ldst.s b/gas/testsuite/gas/aarch64/morello_ldst.s
index 162487f2437f1e6873be07a2a1f7d1e388b75863..d5afdc1855618b00a3384ed687d63df0768e3630 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_ldst.s
+++ b/gas/testsuite/gas/aarch64/morello_ldst.s
@@ -80,7 +80,7 @@ morello_uimm c4, VAREG
 morello_uimm c4, SP_
 
        .macro morello_simm ct, xnsp
-         .irp op, ldur, ldtr, stur, sttr
+         .irp op, ldur, stur
            \op    \ct, [\xnsp, #255]
            \op    \ct, [\xnsp, #-255]
            \op    \ct, [\xnsp, #0]
@@ -90,6 +90,17 @@ morello_uimm c4, SP_
 morello_simm c4, VAREG
 morello_simm c4, SP_
 
+       .macro morello_simm_scale ct, xnsp
+         .irp op, ldtr, sttr
+           \op    \ct, [\xnsp, #4080]
+           \op    \ct, [\xnsp, #-4096]
+           \op    \ct, [\xnsp, #0]
+           \op    \ct, [\xnsp, #16]
+         .endr
+       .endm
+morello_simm_scale c4, VAREG
+morello_simm_scale c4, SP_
+
        .macro morello_simm_pair ct, ct2, xnsp
          .irp op, ldp, stp, ldnp, stnp
            \op    \ct, \ct2, [\xnsp, #1008]

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ed383afdd71dfa739b64a250edfef7e9ed294d42..d868c6d471d925c66666ec29a6a8446e51fc48b8 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2021-09-24  Alex Coplan  <alex.coplan@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Update A64C_INSNs
+       ldtr/sttr to take A64C_ADDR_SIMM9 instead of ADDR_SIMM9
+       operands.
+
 2021-03-17  Luis Machado  <luis.machado@arm.com>
 
        * aarch64-dis.c (enum map_type): Moved to include/opcode/aarch64.h.

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 24f92130254f3687c0ad51560bc306353a652f40..67786d4b5590252cc0fdbb0f929b9615c96f7163 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4093,8 +4093,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("str", 0xa2000400, 0xffe00400, ldst_imm9, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("ldr", 0xa2600800, 0xffe00c00, ldst_regoff, 0, OP2 (Cat, ADDR_REGOFF), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("str", 0xa2200800, 0xffe00c00, ldst_regoff, 0, OP2 (Cat, ADDR_REGOFF), QL2_A64C_CA_ADDR, 0),
-  A64C_INSN ("ldtr", 0xa2400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
-  A64C_INSN ("sttr", 0xa2000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("ldtr", 0xa2400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
+  A64C_INSN ("sttr", 0xa2000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("ldur", 0xa2400000, 0xffe00c00, ldst_unscaled, OP_LDUR_C, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),
   A64C_INSN ("stur", 0xa2000000, 0xffe00c00, ldst_unscaled, OP_STUR_C, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0),