arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode

Enable PCIe0 and PCIe1 instances of PCIe in Root Complex mode of
operation on J784S4 EVM. The lanes of PCIe0 are connected to Serdes1
instance of Serdes while the lanes of PCIe1 are connected to Serdes0
instance of Serdes in J784S4 SoC. Despite both PCIe instances supporting
up to 4 Lanes, since the physical connections to the PCIe connector
corresponding to the PCIe1 instance of PCIe are limited to 2 Lanes on
the J784S4 EVM, update the "num-lanes" property of PCIe1 accordingly.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240529082259.1619695-3-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 41f423dc4eea3f4eacb11c808c6d842d26f1b795..a4a6efcce3620bfa3fec087d9c586b5f4ec76933 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -1325,3 +1325,51 @@
        pinctrl-0 = <&main_mcan4_pins_default>;
        phys = <&transceiver3>;
 };
+
+&serdes0 {
+       status = "okay";
+
+       serdes0_pcie1_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <4>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>,
+                        <&serdes_wiz0 3>, <&serdes_wiz0 4>;
+       };
+};
+
+&serdes_wiz0 {
+       status = "okay";
+};
+
+&pcie1_rc {
+       status = "okay";
+       num-lanes = <2>;
+       reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie1_link>;
+       phy-names = "pcie-phy";
+};
+
+&serdes1 {
+       status = "okay";
+
+       serdes1_pcie0_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+       };
+};
+
+&serdes_wiz1 {
+       status = "okay";
+};
+
+&pcie0_rc {
+       status = "okay";
+       reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes1_pcie0_link>;
+       phy-names = "pcie-phy";
+};