+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-/ {
- aliases {
- spi0 = &qspi;
- };
-
- chosen {
- bootph-pre-ram;
- };
-
- firmware {
- spi0 = &qspi;
- bootph-pre-ram;
- };
-
- memory@40000000 {
- bootph-pre-ram;
- };
-};
-
-&uart0 {
- bootph-pre-ram;
- reg-offset = <0>;
- current-speed = <115200>;
-};
-
-&mmc0 {
- bootph-pre-ram;
-};
-
-&mmc1 {
- bootph-pre-ram;
-};
-
-&qspi {
- bootph-pre-ram;
-
- flash@0 {
- bootph-pre-ram;
- cdns,read-delay = <2>;
- spi-max-frequency = <100000000>;
- };
-};
-
-&syscrg {
- assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
- <&syscrg JH7110_SYSCLK_BUS_ROOT>,
- <&syscrg JH7110_SYSCLK_PERH_ROOT>,
- <&syscrg JH7110_SYSCLK_QSPI_REF>;
- assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
- <&pllclk JH7110_PLLCLK_PLL2_OUT>,
- <&pllclk JH7110_PLLCLK_PLL2_OUT>,
- <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
- assigned-clock-rates = <0>, <0>, <0>, <0>;
-};
-
-&sysgpio {
- bootph-pre-ram;
-};
-
-&mmc0_pins {
- bootph-pre-ram;
- rst-pins {
- bootph-pre-ram;
- };
-};
-
-&mmc1_pins {
- bootph-pre-ram;
- clk-pins {
- bootph-pre-ram;
- };
-
- mmc-pins {
- bootph-pre-ram;
- };
-};
-
-&i2c5_pins {
- bootph-pre-ram;
- i2c-pins {
- bootph-pre-ram;
- };
-};
-
-&i2c5 {
- bootph-pre-ram;
- eeprom@50 {
- bootph-pre-ram;
- compatible = "atmel,24c04";
- reg = <0x50>;
- pagesize = <16>;
- };
-};
* Copyright (C) 2024 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"
* Copyright (C) 2024 StarFive Technology Co., Ltd.
*/
-#include "jh7110-common-u-boot.dtsi"
+#include "jh7110-u-boot.dtsi"
#include "starfive-visionfive2-binman.dtsi"