RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander

The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.

gcc/ChangeLog:

	* config/riscv/riscv-v.h (valid_vec_immediate_p): Add new helper.
	* config/riscv/riscv-v.cc (valid_vec_immediate_p): Ditto.
	(expand_const_vector): Use new helper.
	* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point
	case.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 897b31c069e456ade4d377d51e8c87cc1e811ab7..32349677dc285cbc54beaf1c3ba3c156f4b692de 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -794,6 +794,15 @@ const_vec_all_in_range_p (rtx vec, poly_int64 minval, poly_int64 maxval)
   return true;
 }
 
+/* Returns true if the vector's elements are all duplicates in
+   range -16 ~ 15 integer or 0.0 floating-point.  */
+
+bool
+valid_vec_immediate_p (rtx x)
+{
+  return (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x));
+}
+
 /* Return a const vector of VAL. The VAL can be either const_int or
    const_poly_int.  */
 
@@ -1119,7 +1128,7 @@ expand_const_vector (rtx target, rtx src)
     {
       /* Element in range -16 ~ 15 integer or 0.0 floating-point,
         we use vmv.v.i instruction.  */
-      if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src))
+      if (valid_vec_immediate_p (src))
        {
          rtx ops[] = {result, src};
          emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops);

diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
index 4635b5415c78d65c224c786f1a2648064959d3f6..e7b095f094e6a09d5e754fce1be1d657285e95a5 100644 (file)
--- a/gcc/config/riscv/riscv-v.h
+++ b/gcc/config/riscv/riscv-v.h
@@ -83,6 +83,8 @@ private:
   unsigned int m_inner_bytes_size;
 };
 
+extern bool valid_vec_immediate_p(rtx);
+
 } // namespace riscv_vector
 
 #endif // GCC_RISCV_V_H

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 771ab52625f85e8b7952d55cfed1a88c55105eb3..e9b1b9bc3add2dfbabbff69be356d24f427b7abb 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2158,11 +2158,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
                if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
                    && !immediate_operand (elt, Pmode))
                  return 0;
-               /* Constants from -16 to 15 can be loaded with vmv.v.i.
-                  The Wc0, Wc1 constraints are already covered by the
-                  vi constraint so we do not need to check them here
-                  separately.  */
-               if (satisfies_constraint_vi (x))
+               /* Constants in range -16 ~ 15 integer or 0.0 floating-point
+                  can be emitted using vmv.v.i.  */
+               if (valid_vec_immediate_p (x))
                  return 1;
 
                /* Any int/FP constants can always be broadcast from a