]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
test: Add xfail into slp-reduc-7.c for RVV VLA vectorization
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Wed, 30 Aug 2023 11:49:41 +0000 (19:49 +0800)
committerPan Li <pan2.li@intel.com>
Wed, 30 Aug 2023 12:32:45 +0000 (20:32 +0800)
Like ARM SVE, add RVV variable length xfail.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/slp-reduc-7.c: Add RVV.

gcc/testsuite/gcc.dg/vect/slp-reduc-7.c

index 7a958f24733a1ae942ac31b69866beed1d4a9a1f..a8528ab53ee281ddf2ff14b6731714b0e872fddc 100644 (file)
@@ -57,5 +57,5 @@ int main (void)
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_int_add } } } */
 /* For variable-length SVE, the number of scalar statements in the
    reduction exceeds the number of elements in a 128-bit granule.  */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_no_int_add || { aarch64_sve && vect_variable_length } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_no_int_add || { { aarch64_sve && vect_variable_length } || { riscv_vector && vect_variable_length } } } } } } */
 /* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */