drm/amd/display: Add CM_BYPASS via debug option

[Why]
bypass CM block and MPC ogam for debug or triage use.

[How]
create a new flag cm_bypass_mode, which will set both CM_CONTROL
and MPCC_OGAM_MODE to bypass when set to 1.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 421932ac3b267e93d5c4122abb6d82298cb44f8d..27900297bdcf6553b058d0a3f5eea4e7143004f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -379,6 +379,9 @@ struct dc_debug_options {
         */
        unsigned int force_min_dcfclk_mhz;
        bool disable_timing_sync;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+       bool cm_in_bypass;
+#endif
 };
 
 struct dc_debug_data {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
index e28b8e7bedf59db587366ad77e67c235af35c72d..2d112c316424f535d2312e02fc76f1c45be6ed39 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
@@ -52,7 +52,12 @@ static void dpp2_enable_cm_block(
 {
        struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
 
-       REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
+       unsigned int cm_bypass_mode = 0;
+       //Temp, put CM in bypass mode
+       if (dpp_base->ctx->dc->debug.cm_in_bypass)
+               cm_bypass_mode = 1;
+
+       REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
 }
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 240749e4cf830ad61b31ecc50d5e1ea15f551c17..f4d3008e5efa62d92f12f6be2bd5f79793bf510f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -368,6 +368,11 @@ void apply_DEDCN20_305_wa(
 {
        struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
 
+       if (mpc->ctx->dc->debug.cm_in_bypass) {
+               REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
+               return;
+       }
+
        if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
                /*hw fixed in new review*/
                return;
@@ -390,10 +395,16 @@ void mpc2_set_output_gamma(
        enum dc_lut_mode next_mode;
        struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
 
+       if (mpc->ctx->dc->debug.cm_in_bypass) {
+               REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
+               return;
+       }
+
        if (params == NULL) {
                REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
                return;
        }
+
        current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
        if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
                next_mode = LUT_RAM_B;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 60c671fcf186d87a174508d4aa8a6e6508ad76f5..9b69a06ab46fb1038d9e4bfef9cde57e9c3a0be9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -42,6 +42,7 @@ struct dpp {
 
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
        struct pwl_params shaper_params;
+       bool cm_bypass_mode;
 #endif
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 45b94e319cd4012a408f48e61b566b981c45d0b2..9f00289bda788523a4f7ec27b60e3495f5bc1f2c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -128,6 +128,7 @@ struct mpc {
        struct mpcc mpcc_array[MAX_MPCC];
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
        struct pwl_params blender_params;
+       bool cm_bypass_mode;
 #endif
 };