drm/amdgpu/vcn: don't enable per queue resets on SR-IOV

Power control is only available in bare metal.  SR-IOV
will need a different method.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 5bbce8544fef0249697782054400b6064bc6f282..e6613246d8b8d5a9aea9d779ee17f0456fcc0632 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -241,7 +241,8 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
 
        adev->vcn.supported_reset =
                amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
-       adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
+       if (!amdgpu_sriov_vf(adev))
+               adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 
        if (amdgpu_sriov_vf(adev)) {
                r = amdgpu_virt_alloc_mm_table(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 6000c528ad6aecea825c88f88d851fe49e01c2a3..732e9a9293d26683163bc6ed2f33d78507877cd3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -220,7 +220,8 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
        }
 
        adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
-       adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
+       if (!amdgpu_sriov_vf(adev))
+               adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 
        r = amdgpu_vcn_sysfs_reset_mask_init(adev);
        if (r)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 3d3b4254bd729fbf1f760b0b08d71c478ed607a8..a137bef918ed55da7fa84cde42b8aed153c5a807 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -198,7 +198,8 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
 
        adev->vcn.supported_reset =
                amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
-       adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
+       if (!amdgpu_sriov_vf(adev))
+               adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 
        vcn_v5_0_0_alloc_ip_dump(adev);