rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support

Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
index e84a0943a940df12ad7d914141892b0f7038b5ec..125b08ee8322e26ae91b3e8ef8c1fc398db2eab8 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
        case CLK_CPLL_DIV10:
        case FCLK_DDR_CM0_CORE:
        case ACLK_PHP_ROOT:
+       case CLK_REF_PCIE0_PHY:
+       case CLK_REF_PCIE1_PHY:
                ret = 0;
                break;
 #ifndef CONFIG_SPL_BUILD