arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block

Chipsets before SM8450 have only one broadcast register (Broadcast_OR)
which is used to broadcast writes and check for status bit 0 only in
all channels.
>From SM8450 onwards, a new Broadcast_AND region was added
which checks for status bit 1. This hasn't been updated and Broadcast_OR
region was wrongly being used to check for status bit 1 all along.
Hence mapping Broadcast_AND region's address space to LLCC in SM8550.

Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Link: https://lore.kernel.org/r/9bb6e086adec4d3b2134462d504822fb79b009e7.1717014052.git.quic_uchalich@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 9564963fbabf5589d4f3042449d03526c1d58093..594813538863ce3615343ae6769fc437d4a1d2d3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4311,12 +4311,14 @@
                              <0 0x25200000 0 0x200000>,
                              <0 0x25400000 0 0x200000>,
                              <0 0x25600000 0 0x200000>,
-                             <0 0x25800000 0 0x200000>;
+                             <0 0x25800000 0 0x200000>,
+                             <0 0x25a00000 0 0x200000>;
                        reg-names = "llcc0_base",
                                    "llcc1_base",
                                    "llcc2_base",
                                    "llcc3_base",
-                                   "llcc_broadcast_base";
+                                   "llcc_broadcast_base",
+                                   "llcc_broadcast_and_base";
                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
                };