s390: Extend two/four element integer vectors

For the moment I deliberately left out one-element QHS vectors since it
is unclear whether these are pathological cases or whether they are
really used.  If we ever get an extend for V1DI -> V1TI we should
reconsider this.

As a side-effect this fixes PR115261.

gcc/ChangeLog:

	PR target/115261
	* config/s390/s390.md (any_extend,extend_insn,zero_extend):
	New code attributes and code iterator.
	* config/s390/vector.md (V_EXTEND): New mode iterator.
	(<extend_insn><V_EXTEND:mode><vec_2x_wide>2): New insn.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/vec-extend-1.c: New test.
	* gcc.target/s390/vector/vec-extend-2.c: New test.

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index c607dce3cf0fd882f2747e462935408db7e329af..1311a5f01cf37ce809db31cd0983165a95618a4f 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -602,6 +602,10 @@
 
 (define_attr "relative_long" "no,yes" (const_string "no"))
 
+(define_code_attr extend_insn [(sign_extend "extend") (zero_extend "zero_extend")])
+(define_code_attr zero_extend [(sign_extend "") (zero_extend "l")])
+(define_code_iterator any_extend [sign_extend zero_extend])
+
 ;; Pipeline description for z900.
 (include "2064.md")
 

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index ed4742d93c91f7fa9e90c1a3d0a6e81823cf4776..a931a4b1b17e68f64da78bd37359b15748c36e69 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -87,6 +87,8 @@
 ; 32 bit int<->fp vector conversion instructions are available since VXE2 (z15).
 (define_mode_iterator VX_VEC_CONV_BFP [V2DF (V4SF "TARGET_VXE2")])
 
+(define_mode_iterator VI_EXTEND [V2QI V2HI V2SI V4QI V4HI])
+
 ; Empty string for all but TImode.  This is used to hide the TImode
 ; expander name in case it is defined already.  See addti3 for an
 ; example.
@@ -195,13 +197,20 @@
                                (V1DF "V2DF") (V2DF "V4DF")])
 
 ; Vector with widened element size and the same number of elements.
-(define_mode_attr vec_2x_wide [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI "V8HI") (V16QI "V16HI")
+(define_mode_attr VEC_2X_WIDE [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI "V8HI") (V16QI "V16HI")
                               (V1HI "V1SI") (V2HI "V2SI") (V4HI "V4SI") (V8HI "V8SI")
                               (V1SI "V1DI") (V2SI "V2DI") (V4SI "V4DI")
                               (V1DI "V1TI") (V2DI "V2TI")
                               (V1SF "V1DF") (V2SF "V2DF") (V4SF "V4DF")
                               (V1DF "V1TF") (V2DF "V2TF")])
 
+(define_mode_attr vec_2x_wide [(V1QI "v1hi") (V2QI "v2hi") (V4QI "v4hi") (V8QI "v8hi") (V16QI "v16hi")
+                              (V1HI "v1si") (V2HI "v2si") (V4HI "v4si") (V8HI "v8si")
+                              (V1SI "v1di") (V2SI "v2di") (V4SI "v4di")
+                              (V1DI "v1ti") (V2DI "v2ti")
+                              (V1SF "v1df") (V2SF "v2df") (V4SF "v4df")
+                              (V1DF "v1tf") (V2DF "v2tf")])
+
 ; Vector with half the element size AND half the number of elements.
 (define_mode_attr vec_halfhalf
   [(V2HI "V2QI") (V4HI "V4QI") (V8HI "V8QI")
@@ -1604,7 +1613,7 @@
                             UNSPEC_VEC_UMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-        (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+        (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
         (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1623,7 +1632,7 @@
                             UNSPEC_VEC_UMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-        (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+        (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
         (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1642,7 +1651,7 @@
                             UNSPEC_VEC_SMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-        (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+        (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
         (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1661,7 +1670,7 @@
                             UNSPEC_VEC_SMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-        (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+        (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
         (match_dup 5)))]
   "TARGET_VX"
  {
@@ -2375,6 +2384,16 @@
   "vpkls<bhfgq>\t%0,%1,%2"
   [(set_attr "op_type" "VRR")])
 
+;; vector unpack / extend
+
+(define_insn "<extend_insn><VI_EXTEND:mode><vec_2x_wide>2"
+  [(set (match_operand:<VEC_2X_WIDE> 0 "register_operand" "=v")
+       (any_extend:<VEC_2X_WIDE>
+        (match_operand:VI_EXTEND 1 "register_operand" "v")))]
+  "TARGET_VX"
+  "vup<zero_extend>h<bhfgq>\t%0,%1"
+  [(set_attr "op_type" "VRR")])
+
 ;; vector unpack v16qi
 
 ; signed

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-extend-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-extend-1.c
new file mode 100644 (file)
index 0000000..5f4f2c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-extend-1.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z13 -mzarch" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+typedef signed char v2qi __attribute__ ((vector_size (2)));
+typedef short v2hi __attribute__ ((vector_size (4)));
+typedef int v2si __attribute__ ((vector_size (8)));
+typedef long long v2di __attribute__ ((vector_size (16)));
+
+typedef unsigned char uv2qi __attribute__ ((vector_size (2)));
+typedef unsigned short uv2hi __attribute__ ((vector_size (4)));
+typedef unsigned int uv2si __attribute__ ((vector_size (8)));
+typedef unsigned long long uv2di __attribute__ ((vector_size (16)));
+
+/*
+** extendv2qiv2hi2:
+**     vuphb   %v24,%v24
+**     br      %r14
+*/
+
+v2hi extendv2qiv2hi2 (v2qi x)
+{
+  return __builtin_convertvector (x, v2hi);
+}
+
+/*
+** extendv2hiv2si2:
+**     vuphh   %v24,%v24
+**     br      %r14
+*/
+
+v2si extendv2hiv2si2 (v2hi x)
+{
+  return __builtin_convertvector (x, v2si);
+}
+
+/*
+** extendv2siv2di2:
+**     vuphf   %v24,%v24
+**     br      %r14
+*/
+
+v2di extendv2siv2di2 (v2si x)
+{
+  return __builtin_convertvector (x, v2di);
+}
+
+/*
+** extenduv2qiuv2hi2:
+**     vuplhb  %v24,%v24
+**     br      %r14
+*/
+
+uv2hi extenduv2qiuv2hi2 (uv2qi x)
+{
+  return __builtin_convertvector (x, uv2hi);
+}
+
+/*
+** extenduv2hiuv2si2:
+**     vuplhh  %v24,%v24
+**     br      %r14
+*/
+
+uv2si extenduv2hiuv2si2 (uv2hi x)
+{
+  return __builtin_convertvector (x, uv2si);
+}
+
+/*
+** extenduv2siuv2di2:
+**     vuplhf  %v24,%v24
+**     br      %r14
+*/
+
+uv2di extenduv2siuv2di2 (uv2si x)
+{
+  return __builtin_convertvector (x, uv2di);
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-extend-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-extend-2.c
new file mode 100644 (file)
index 0000000..d9c07ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-extend-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z13 -mzarch" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+typedef signed char v4qi __attribute__ ((vector_size (4)));
+typedef short v4hi __attribute__ ((vector_size (8)));
+typedef int v4si __attribute__ ((vector_size (16)));
+
+typedef unsigned char uv4qi __attribute__ ((vector_size (4)));
+typedef unsigned short uv4hi __attribute__ ((vector_size (8)));
+typedef unsigned int uv4si __attribute__ ((vector_size (16)));
+
+/*
+** extendv4qiv4hi2:
+**     vuphb   %v24,%v24
+**     br      %r14
+*/
+
+v4hi extendv4qiv4hi2 (v4qi x)
+{
+  return __builtin_convertvector (x, v4hi);
+}
+
+/*
+** extendv4hiv4si2:
+**     vuphh   %v24,%v24
+**     br      %r14
+*/
+
+v4si extendv4hiv4si2 (v4hi x)
+{
+  return __builtin_convertvector (x, v4si);
+}
+
+/*
+** extenduv4qiuv4hi2:
+**     vuplhb  %v24,%v24
+**     br      %r14
+*/
+
+uv4hi extenduv4qiuv4hi2 (uv4qi x)
+{
+  return __builtin_convertvector (x, uv4hi);
+}
+
+/*
+** extenduv4hiuv4si2:
+**     vuplhh  %v24,%v24
+**     br      %r14
+*/
+
+uv4si extenduv4hiuv4si2 (uv4hi x)
+{
+  return __builtin_convertvector (x, uv4si);
+}