arm: socfpga: spl: Notify SDM on FSBL execution

Send out "HPS_STAGE_NOTIFY" mailbox command to the
Secure Device Manager (SDM) in SPL to inform SDM on
FSBL execution.

This is necessary for the SDM to recognize that the
FSBL stage has begun its execution and should be
made as early as possible in the FSBL process.

Therefore, the mailbox will initialize and send out
the notification right after the completion of timer
initialization.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 52617a39ccaf96b1a655906f41b0083d597e9b3a..91c27a5543d61004bf1feb679d6a05bda2d0e5c6 100644 (file)
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -50,6 +50,10 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
+       mbox_init();
+
+       mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
        sysmgr_pinmux_init();
 
        ret = uclass_get_device(UCLASS_CLK, 0, &dev);
@@ -77,8 +81,6 @@ void board_init_f(ulong dummy)
        }
 #endif
 
-       mbox_init();
-
 #ifdef CONFIG_CADENCE_QSPI
        mbox_qspi_open();
 #endif

diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
index 3451611082dcd7bfba6442c6594350b46e14007a..a9aad5350d25fb6d6d65e89402901f43471bdb76 100644 (file)
--- a/arch/arm/mach-socfpga/spl_agilex5.c
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -62,6 +62,10 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
+       mbox_init();
+
+       mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
        ret = uclass_get_device(UCLASS_CLK, 0, &dev);
        if (ret) {
                debug("Clock init failed: %d\n", ret);
@@ -100,8 +104,6 @@ void board_init_f(ulong dummy)
                }
        }
 
-       mbox_init();
-
        if (IS_ENABLED(CONFIG_CADENCE_QSPI))
                mbox_qspi_open();
 

diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c
index 5ff137e5c6fb05754d03ec3cf79c1194040585ed..81283ef71620034ca173048c27cefed6a62c32d2 100644 (file)
--- a/arch/arm/mach-socfpga/spl_n5x.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -49,6 +49,10 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
+       mbox_init();
+
+       mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
        sysmgr_pinmux_init();
 
        preloader_console_init();
@@ -84,8 +88,6 @@ void board_init_f(ulong dummy)
        }
 #endif
 
-       mbox_init();
-
 #ifdef CONFIG_CADENCE_QSPI
        mbox_qspi_open();
 #endif

diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 53852cb744391886dba962e7df197af408018d22..fa83ff96adc862afb2209ba91c031ce89517e97b 100644 (file)
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -52,6 +52,10 @@ void board_init_f(ulong dummy)
        socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
        timer_init();
 
+       mbox_init();
+
+       mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
        sysmgr_pinmux_init();
 
        /* configuring the HPS clocks */
@@ -84,8 +88,6 @@ void board_init_f(ulong dummy)
                }
 #endif
 
-       mbox_init();
-
 #ifdef CONFIG_CADENCE_QSPI
        mbox_qspi_open();
 #endif