--- /dev/null
+From 3b5e50edaf500f392f4a372296afc0b99ffa7e70 Mon Sep 17 00:00:00 2001
+From: Ralf Baechle <ralf@linux-mips.org>
+Date: Mon, 22 Apr 2013 17:57:54 +0200
+Subject: Revert "MIPS: page.h: Provide more readable definition for PAGE_MASK."
+
+From: Ralf Baechle <ralf@linux-mips.org>
+
+commit 3b5e50edaf500f392f4a372296afc0b99ffa7e70 upstream.
+
+This reverts commit c17a6554782ad531f4713b33fd6339ba67ef6391.
+
+Manuel Lauss writes:
+
+lmo commit c17a6554 (MIPS: page.h: Provide more readable definition for
+PAGE_MASK) apparently breaks ioremap of 36-bit addresses on my Alchemy
+systems (PCI and PCMCIA) The reason is that in arch/mips/mm/ioremap.c
+line 157 (phys_addr &= PAGE_MASK) bits 32-35 are cut off. Seems the
+new PAGE_MASK is explicitly 32bit, or one could make it signed instead
+of unsigned long.
+
+From: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/mips/include/asm/page.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/page.h
++++ b/arch/mips/include/asm/page.h
+@@ -31,7 +31,7 @@
+ #define PAGE_SHIFT 16
+ #endif
+ #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
+-#define PAGE_MASK (~(PAGE_SIZE - 1))
++#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
+
+ #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+ #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
vm-convert-mtdchar-mmap-to-vm_iomap_memory-helper.patch
btrfs-make-sure-nbytes-are-right-after-log-replay.patch
s390-move-dummy-io_remap_pfn_range-to-asm-pgtable.h.patch
+revert-mips-page.h-provide-more-readable-definition-for-page_mask.patch