test: Recover sdiv_pow2 check and remove test of RISC-V

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/vect-sdiv-pow2-1.c: Recover scan check.
	* lib/target-supports.exp: Remove riscv.

diff --git a/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c b/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c
index 8056c2a6748fe2337d480c0e2185de728926cdb4..49ecbe216f2740329d5cd2169527a9aeb7ab844c 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c
@@ -79,5 +79,5 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump "vect_recog_divmod_pattern: detected" "vect" } } */
+/* { dg-final { scan-tree-dump {\.DIV_POW2} "vect" { target vect_sdiv_pow2_si } } } */
 /* { dg-final { scan-tree-dump-times "vectorized 1 loop" 18 "vect" { target vect_sdiv_pow2_si } } } */

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 0317fc102ef729c1cbabae60311360150998517a..8f6cdf16661cfd0f87bd7b8631688f09efd64345 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8077,9 +8077,7 @@ proc check_effective_target_vect_mulhrs_hi {} {
 
 proc check_effective_target_vect_sdiv_pow2_si {} {
     return [expr { ([istarget aarch64*-*-*]
-                   && [check_effective_target_aarch64_sve])
-                  || ([istarget riscv*-*-*]
-                      && [check_effective_target_riscv_v]) }]
+                   && [check_effective_target_aarch64_sve]) }]
 }
 
 # Return 1 if the target plus current options supports a vector