PowerPC: Add support for RFC02680 - PQC Acceleration Instructions

opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xvadduwm, xvadduhm, xvsubuwm,
	xvsubuhm, xvmuluwm, xvmuluhm, xvmulhsw, xvmulhsh, xvmulhuw,
	xvmulhuh.
gas/
	* testsuite/gas/ppc/future.s: New test.
	* testsuite/gas/ppc/future.d: Likewise.

diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
index c0d9080c04f62d21f5ea11bc6e7e1962284acf62..d639e8c618fff5b047dfa772ee71e664211ff271 100644 (file)
--- a/gas/testsuite/gas/ppc/future.d
+++ b/gas/testsuite/gas/ppc/future.d
@@ -25,4 +25,14 @@ Disassembly of section \.text:
 .*:    (9a 8d 2a 7d|7d 2a 8d 9a)       stxvprl vs40,r10,r17
 .*:    (da 95 6a 7d|7d 6a 95 da)       stxvprll vs42,r10,r18
 .*:    (c6 9d e9 f3|f3 e9 9d c6)       xvrlw   vs31,vs41,vs51
+.*:    (1e a4 ca f3|f3 ca a4 1e)       xvadduwm vs30,vs42,vs52
+.*:    (5e ac ca f3|f3 ca ac 5e)       xvadduhm vs30,vs42,vs53
+.*:    (9e b4 ab f3|f3 ab b4 9e)       xvsubuwm vs29,vs43,vs54
+.*:    (d9 f4 e0 f3|f3 e0 f4 d9)       xvsubuhm vs63,vs0,vs30
+.*:    (1e e5 c8 f3|f3 c8 e5 1e)       xvmuluwm vs30,vs40,vs60
+.*:    (5f f5 9d f3|f3 9d f5 5f)       xvmuluhm vs60,vs61,vs62
+.*:    (9f 25 43 f0|f0 43 25 9f)       xvmulhsw vs34,vs35,vs36
+.*:    (d8 1d 22 f0|f0 22 1d d8)       xvmulhsh vs1,vs2,vs3
+.*:    (90 b3 95 f2|f2 95 b3 90)       xvmulhuw vs20,vs21,vs22
+.*:    (d6 a3 8a f2|f2 8a a3 d6)       xvmulhuh vs20,vs42,vs52
 #pass

diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
index 4e782e8764d2453bfb8dd736c048af5edc47ea66..9abf6b3de7b30b88d793e7bc5b92068d348f5c91 100644 (file)
--- a/gas/testsuite/gas/ppc/future.s
+++ b/gas/testsuite/gas/ppc/future.s
@@ -17,3 +17,13 @@ _start:
        stxvprl  40,10,17
        stxvprll 42,10,18
        xvrlw    31,41,51
+       xvadduwm 30,42,52
+       xvadduhm 30,42,53
+       xvsubuwm 29,43,54
+       xvsubuhm 63,0,30
+       xvmuluwm 30,40,60
+       xvmuluhm 60,61,62
+       xvmulhsw 34,35,36
+       xvmulhsh 1,2,3
+       xvmulhuw 20,21,22
+       xvmulhuh 20,42,52

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 705b5d78d84284319dad43e0ca42c2d540fbf035..ed5675b4f93ed30992bed79e7c0d7c9ea3764e64 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -9320,6 +9320,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xvredp",     XX2(60,218),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xvmuldp",    XX3(60,112),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xvmsubadp",  XX3(60,113),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmulhuw",   XX3(60,114),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xvcmpgedp",  XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xvcvuxwdp",  XX2(60,232),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
@@ -9328,38 +9329,45 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xvrdpic",    XX2(60,235),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xvdivdp",    XX3(60,120),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xvmsubmdp",  XX3(60,121),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmulhuh",   XX3(60,122),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xvcvsxwdp",  XX2(60,248),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xvrdpim",    XX2(60,249),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xvtdivdp",   XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCVLE,         {BF, XA6, XB6}},
 {"xsmaxcdp",   XX3(60,128),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmaddasp", XX3(60,129),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
 {"xxland",     XX3(60,130),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvadduwm",   XX3(60,131),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvdpsp",   XX2(60,265),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xscvdpspn",  XX2(60,267),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
 {"xsmincdp",   XX3(60,136),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmaddmsp", XX3(60,137),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
 {"xxlandc",    XX3(60,138),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvadduhm",   XX3(60,139),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsrsp",      XX2(60,281),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
 {"xsmaxjdp",   XX3(60,144),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmsubasp", XX3(60,145),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
 {"xxmr",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCVLE|EXT,     {XT6, XAB6}},
 {"xxlor",      XX3(60,146),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvsubuwm",   XX3(60,147),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvuxdsp",  XX2(60,296),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
 {"xststdcsp",  XX2(60,298),    XX2BFD_MASK, PPCVSX3,   PPCVLE,         {BF, XB6, DCMX}},
 {"xsminjdp",   XX3(60,152),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmsubmsp", XX3(60,153),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
 {"xxlxor",     XX3(60,154),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvsubuhm",   XX3(60,155),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvsxdsp",  XX2(60,312),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
 {"xsmaxdp",    XX3(60,160),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmaddadp", XX3(60,161),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xxlnot",     XX3(60,162),    XX3_MASK,    PPCVSX,    PPCVLE|EXT,     {XT6, XAB6}},
 {"xxlnor",     XX3(60,162),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmuluwm",   XX3(60,163),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvdpuxds", XX2(60,328),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xscvspdp",   XX2(60,329),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xscvspdpn",  XX2(60,331),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
 {"xsmindp",    XX3(60,168),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmaddmdp", XX3(60,169),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xxlorc",     XX3(60,170),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xvmuluhm",   XX3(60,171),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvdpsxds", XX2(60,344),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xsabsdp",    XX2(60,345),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xsxexpdp",   XX2VA(60,347,0),XX2_MASK|1,  PPCVSX3,   PPCVLE,         {RT, XB6}},
@@ -9369,12 +9377,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xscpsgndp",  XX3(60,176),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmsubadp", XX3(60,177),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xxlnand",    XX3(60,178),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xvmulhsw",   XX3(60,179),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvuxddp",  XX2(60,360),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xsnabsdp",   XX2(60,361),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xststdcdp",  XX2(60,362),    XX2BFD_MASK, PPCVSX3,   PPCVLE,         {BF, XB6, DCMX}},
 {"xvrlw",      XX3(60,184),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsnmsubmdp", XX3(60,185),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
 {"xxleqv",     XX3(60,186),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xvmulhsh",   XX3(60,187),    XX3_MASK,    PPCVSXF,   PPCVLE,         {XT6, XA6, XB6}},
 {"xscvsxddp",  XX2(60,376),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xsnegdp",    XX2(60,377),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
 {"xvmaxsp",    XX3(60,192),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},