mmc: sdhci-of-dwcmshc: move two rk35xx functions

This patch just move dwcmshc_rk35xx_init() and
dwcmshc_rk35xx_postinit() to put the functions
of rk35xx together as much as possible.

This change is an intermediate process before
further modification.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Drew Fustini <drew@pdp7.com> # TH1520
Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/54204702d5febd3e867eb3544c36919fe4140a88.1722847198.git.unicorn_wang@outlook.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 35401616fb2eff7de48bb329b6ff1d70cad751b1..a002636d51fd80361b4524e4f5607da10979f7c2 100644 (file)
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -711,6 +711,51 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
        sdhci_reset(host, mask);
 }
 
+static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
+{
+       static const char * const clk_ids[] = {"axi", "block", "timer"};
+       struct rk35xx_priv *priv = dwc_priv->priv;
+       int err;
+
+       priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
+       if (IS_ERR(priv->reset)) {
+               err = PTR_ERR(priv->reset);
+               dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
+               return err;
+       }
+
+       err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
+                                           ARRAY_SIZE(clk_ids), clk_ids);
+       if (err)
+               return err;
+
+       if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
+                               &priv->txclk_tapnum))
+               priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
+
+       /* Disable cmd conflict check */
+       sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
+       /* Reset previous settings */
+       sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
+       sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
+
+       return 0;
+}
+
+static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
+{
+       /*
+        * Don't support highspeed bus mode with low clk speed as we
+        * cannot use DLL for this condition.
+        */
+       if (host->mmc->f_max <= 52000000) {
+               dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
+                        host->mmc->f_max);
+               host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
+               host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
+       }
+}
+
 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)
 {
        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -1064,51 +1109,6 @@ dsbl_cqe_caps:
        host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD);
 }
 
-static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
-{
-       static const char * const clk_ids[] = {"axi", "block", "timer"};
-       struct rk35xx_priv *priv = dwc_priv->priv;
-       int err;
-
-       priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
-       if (IS_ERR(priv->reset)) {
-               err = PTR_ERR(priv->reset);
-               dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
-               return err;
-       }
-
-       err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
-                                           ARRAY_SIZE(clk_ids), clk_ids);
-       if (err)
-               return err;
-
-       if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
-                               &priv->txclk_tapnum))
-               priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
-
-       /* Disable cmd conflict check */
-       sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
-       /* Reset previous settings */
-       sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
-       sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
-
-       return 0;
-}
-
-static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
-{
-       /*
-        * Don't support highspeed bus mode with low clk speed as we
-        * cannot use DLL for this condition.
-        */
-       if (host->mmc->f_max <= 52000000) {
-               dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
-                        host->mmc->f_max);
-               host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
-               host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
-       }
-}
-
 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
        {
                .compatible = "rockchip,rk3588-dwcmshc",