drm/i915: Relocate vlv_wait_port_ready()

While vlv_wait_port_ready() doens't directly talk to the VLV/CHV
DPIO PHY, the signals it's looking for do come from the PHY. So
it seems appropriate to relocate it into intel_dpio_phy.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213150220.13580-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 80d375ed7d1892f3905c5d3488868f98c564d33f..d83024c17c3cf00bfdbc2dc050e449b605b8ce7e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -473,40 +473,6 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
                assert_plane_disabled(plane);
 }
 
-void vlv_wait_port_ready(struct intel_display *display,
-                        struct intel_digital_port *dig_port,
-                        unsigned int expected_mask)
-{
-       u32 port_mask;
-       i915_reg_t dpll_reg;
-
-       switch (dig_port->base.port) {
-       default:
-               MISSING_CASE(dig_port->base.port);
-               fallthrough;
-       case PORT_B:
-               port_mask = DPLL_PORTB_READY_MASK;
-               dpll_reg = DPLL(display, 0);
-               break;
-       case PORT_C:
-               port_mask = DPLL_PORTC_READY_MASK;
-               dpll_reg = DPLL(display, 0);
-               expected_mask <<= 4;
-               break;
-       case PORT_D:
-               port_mask = DPLL_PORTD_READY_MASK;
-               dpll_reg = DPIO_PHY_STATUS;
-               break;
-       }
-
-       if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
-               drm_WARN(display->drm, 1,
-                        "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
-                        dig_port->base.base.base.id, dig_port->base.base.name,
-                        intel_de_read(display, dpll_reg) & port_mask,
-                        expected_mask);
-}
-
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 {
        struct intel_display *display = to_intel_display(new_crtc_state);

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1b3c8f834a8e89a8c5b0f441a4281e3956ad5b05..b6d1aa05309f3327e7451eac915e1c01fd9ed1c1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -486,9 +486,6 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder);
 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
 
 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
-void vlv_wait_port_ready(struct intel_display *display,
-                        struct intel_digital_port *dig_port,
-                        unsigned int expected_mask);
 
 bool intel_fuzzy_clock_check(int clock1, int clock2);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 5f88702818d3129a76c8197bb45f3b74309ad029..968b795206b3bb89c9f1775f4580546c1f5c181b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1156,3 +1156,37 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
        vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
        vlv_dpio_put(dev_priv);
 }
+
+void vlv_wait_port_ready(struct intel_display *display,
+                        struct intel_digital_port *dig_port,
+                        unsigned int expected_mask)
+{
+       u32 port_mask;
+       i915_reg_t dpll_reg;
+
+       switch (dig_port->base.port) {
+       default:
+               MISSING_CASE(dig_port->base.port);
+               fallthrough;
+       case PORT_B:
+               port_mask = DPLL_PORTB_READY_MASK;
+               dpll_reg = DPLL(display, 0);
+               break;
+       case PORT_C:
+               port_mask = DPLL_PORTC_READY_MASK;
+               dpll_reg = DPLL(display, 0);
+               expected_mask <<= 4;
+               break;
+       case PORT_D:
+               port_mask = DPLL_PORTD_READY_MASK;
+               dpll_reg = DPIO_PHY_STATUS;
+               break;
+       }
+
+       if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
+               drm_WARN(display->drm, 1,
+                        "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
+                        dig_port->base.base.base.id, dig_port->base.base.name,
+                        intel_de_read(display, dpll_reg) & port_mask,
+                        expected_mask);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index a829391655464ae9d6788f88bab3e367dd999b7b..15596407fe87394b9335a5d1d595664c6d7cb664 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -72,6 +72,9 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
                                const struct intel_crtc_state *crtc_state);
 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
                         const struct intel_crtc_state *old_crtc_state);
+void vlv_wait_port_ready(struct intel_display *display,
+                        struct intel_digital_port *dig_port,
+                        unsigned int expected_mask);
 #else
 static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
                                           enum dpio_phy *phy, enum dpio_channel *ch)
@@ -170,6 +173,11 @@ static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder,
                                       const struct intel_crtc_state *old_crtc_state)
 {
 }
+static inline void vlv_wait_port_ready(struct intel_display *display,
+                                      struct intel_digital_port *dig_port,
+                                      unsigned int expected_mask)
+{
+}
 #endif
 
 #endif /* __INTEL_DPIO_PHY_H__ */