[(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
+(define_insn "*xop_pcmov_<mode>"
+ [(set (match_operand:V4F_64 0 "register_operand" "=x")
+ (if_then_else:V4F_64
+ (match_operand:V4F_64 3 "register_operand" "x")
+ (match_operand:V4F_64 1 "register_operand" "x")
+ (match_operand:V4F_64 2 "register_operand" "x")))]
+ "TARGET_XOP && TARGET_MMX_WITH_SSE"
+ "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "type" "sse4arg")
+ (set_attr "mode" "TI")])
+
(define_insn "*xop_pcmov_<mode>"
[(set (match_operand:VI_16_32 0 "register_operand" "=x")
(if_then_else:VI_16_32
[(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
+(define_insn "*xop_pcmov_<mode>"
+ [(set (match_operand:V2F_32 0 "register_operand" "=x")
+ (if_then_else:V2F_32
+ (match_operand:V2F_32 3 "register_operand" "x")
+ (match_operand:V2F_32 1 "register_operand" "x")
+ (match_operand:V2F_32 2 "register_operand" "x")))]
+ "TARGET_XOP"
+ "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "type" "sse4arg")
+ (set_attr "mode" "TI")])
+
;; XOP permute instructions
(define_insn "mmx_ppermv64"
[(set (match_operand:V8QI 0 "register_operand" "=x")
--- /dev/null
+typedef _Float16 v4hf __attribute__((vector_size(8)));
+typedef short v4hi __attribute__((vector_size(8)));
+typedef _Float16 v2hf __attribute__((vector_size(4)));
+typedef short v2hi __attribute__((vector_size(4)));
+
+typedef __bf16 v4bf __attribute__((vector_size(8)));
+typedef __bf16 v2bf __attribute__((vector_size(4)));
+
+v4hf foo(v4hf a, v4hf b, v4hi c)
+{
+ return c ? a : b;
+}
+
+v2hf foo1(v2hf a, v2hf b, v2hi c)
+{
+ return c ? a : b;
+}
+
+v4bf foo(v4bf a, v4bf b, v4hi c)
+{
+ return c ? a : b;
+}
+
+v2bf foo1(v2bf a, v2bf b, v2hi c)
+{
+ return c ? a : b;
+}