clk: imx: fracn-gppll: update rate table

- Add 1039.5MHz clock for video PLL to fulfill the LVDS display
  148.5MHz * 7 requirement
- Add 800MHz clock for ARM PLL

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240607133347.3291040-16-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 1becba2b62d0beb02fedcea912a073eadf14f525..591e0364ee5c113859a7b6271c8c11e98a0e0ffc 100644 (file)
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -78,6 +78,7 @@ struct clk_fracn_gppll {
  * The Fvco should be in range 2.5Ghz to 5Ghz
  */
 static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
+       PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
        PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
        PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
        PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
@@ -106,6 +107,7 @@ static const struct imx_fracn_gppll_rate_table int_tbl[] = {
        PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
        PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
        PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
+       PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
 };
 
 struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {