Fix sparc opcode encoding for 4-arg crypto instructions.

include/opcode

	* sparc.h (F3F4): New macro.

opcodes

	* sparc-opc.c (4-argument crypto instructions): Fix encoding using
	F3F4 macro.

gas/testsuite

	* gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index bf5c3fc1d67963fe4c265be247a00ce21be62a6d..328cdb08f83e018da5a550b8b5bf2b5fa077bf48 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2012-08-21  David S. Miller  <davem@davemloft.net>
+
+       * gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions.
+
 2012-08-20  Edmar Wienskoski  <edmar@freescale.com>
 
        * gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw,

diff --git a/gas/testsuite/gas/sparc/crypto.d b/gas/testsuite/gas/sparc/crypto.d
index 734317d6ecff4e59ce2a5cfed60c84607d8a42dd..daebb6557b0beb827312512a5353aa90afd62e0a 100644 (file)
--- a/gas/testsuite/gas/sparc/crypto.d
+++ b/gas/testsuite/gas/sparc/crypto.d
@@ -13,27 +13,27 @@ Disassembly of section .text:
    c:  81 b0 28 60     sha512 
   10:  8d b0 a8 e4     crc32c  %f2, %f4, %f6
   14:  91 b1 26 06     aes_kexpand0  %f4, %f6, %f8
-  18:  94 41 8f 08     aes_kexpand1  %f6, %f8, 0x7, %f10
-  1c:  94 41 8d 08     aes_kexpand1  %f6, %f8, 0x6, %f10
+  18:  94 c9 8f 08     aes_kexpand1  %f6, %f8, 0x7, %f10
+  1c:  94 c9 8d 08     aes_kexpand1  %f6, %f8, 0x6, %f10
   20:  99 b2 26 2a     aes_kexpand2  %f8, %f10, %f12
-  24:  a0 42 9c 0c     aes_eround01  %f10, %f12, %f14, %f16
-  28:  a4 43 20 2e     aes_eround23  %f12, %f14, %f16, %f18
-  2c:  a8 43 a4 50     aes_dround01  %f14, %f16, %f18, %f20
-  30:  ac 44 28 72     aes_dround23  %f16, %f18, %f20, %f22
-  34:  b0 44 ac 94     aes_eround01_l  %f18, %f20, %f22, %f24
-  38:  b4 45 30 b6     aes_eround23_l  %f20, %f22, %f24, %f26
-  3c:  b8 45 b4 d8     aes_dround01_l  %f22, %f24, %f26, %f28
-  40:  bc 46 38 fa     aes_dround23_l  %f24, %f26, %f28, %f30
+  24:  a0 ca 9c 0c     aes_eround01  %f10, %f12, %f14, %f16
+  28:  a4 cb 20 2e     aes_eround23  %f12, %f14, %f16, %f18
+  2c:  a8 cb a4 50     aes_dround01  %f14, %f16, %f18, %f20
+  30:  ac cc 28 72     aes_dround23  %f16, %f18, %f20, %f22
+  34:  b0 cc ac 94     aes_eround01_l  %f18, %f20, %f22, %f24
+  38:  b4 cd 30 b6     aes_eround23_l  %f20, %f22, %f24, %f26
+  3c:  b8 cd b4 d8     aes_dround01_l  %f22, %f24, %f26, %f28
+  40:  bc ce 38 fa     aes_dround23_l  %f24, %f26, %f28, %f30
   44:  87 b0 66 80     des_ip  %f32, %f34
   48:  8b b0 e6 a0     des_iip  %f34, %f36
   4c:  8f b1 66 c7     des_kexpand  %f36, 7, %f38
-  50:  9a 41 d7 29     des_round  %f38, %f40, %f42, %f44
+  50:  9a c9 d7 29     des_round  %f38, %f40, %f42, %f44
   54:  9f b2 e7 0d     kasumi_fi_fi  %f42, %f44, %f46
-  58:  a6 43 63 4f     kasumi_fl_xor  %f44, %f46, %f48, %f50
-  5c:  aa 43 e7 71     kasumi_fi_xor  %f46, %f48, %f50, %f52
+  58:  a6 cb 63 4f     kasumi_fl_xor  %f44, %f46, %f48, %f50
+  5c:  aa cb e7 71     kasumi_fi_xor  %f46, %f48, %f50, %f52
   60:  af b4 e7 95     camellia_fi  %f50, %f52, %f54
   64:  b3 b5 67 b7     camellia_fli  %f52, %f54, %f56
-  68:  ba 45 f7 99     camellia_f  %f54, %f56, %f58, %f60
+  68:  ba cd f7 99     camellia_f  %f54, %f56, %f58, %f60
   6c:  81 b0 29 00     mpmul  0
   70:  81 b0 29 01     mpmul  1
   74:  81 b0 29 02     mpmul  2

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index c847cb284437d24d4c155f89646c3c5b1a614deb..e0b0673bed08ac1f2213ee12523aec6f8e30e5f1 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2012-08-21  David S. Miller  <davem@davemloft.net>
+
+       * sparc.h (F3F4): New macro.
+
 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
             Laurent Desnogues  <laurent.desnogues@arm.com>
             Jim MacArthur  <jim.macarthur@arm.com>

diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index b1c5e42ad104eb3b59268e9b8940bc8b8f7636c5..892776900273376fd5896360d5cf7a0c378a09e3 100644 (file)
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -234,6 +234,7 @@ typedef struct sparc_opcode
 #define OPF_LOW5(x)    OPF ((x) & 0x1f)     /* V9.  */
 #define OPF_LOW4(x)    OPF ((x) & 0xf)      /* V9.  */
 #define F3F(x, y, z)   (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
+#define F3F4(x, y, z)  (OP (x) | OP3 (y) | OPF_LOW4 (z))
 #define F3I(x)         (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
 #define F2(x, y)       (OP (x) | OP2(y))    /* Format 2 insns.  */
 #define F3(x, y, z)    (OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dac1ed9db561d0e995db6c57f0ed3da8daa7e9c3..b6a9acce443b7a559781766c037ee281e84851f2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-08-21  David S. Miller  <davem@davemloft.net>
+
+       * sparc-opc.c (4-argument crypto instructions): Fix encoding using
+       F3F4 macro.
+
 2012-08-20  Edmar Wienskoski  <edmar@freescale.com>
 
        * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index b2e5344e540367f869b969a72eab0ad510f6233a..87634ae18a158d334cd28011728d0ad61f5b00cd 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1960,19 +1960,19 @@ SLCBCC("cbnefr", 15),
 { "mpmul",      F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
 { "montmul",    F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
 { "montsqr",    F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
-{"aes_eround01",  F2(2, 0x19)|OPF_LOW4(0), F2(~2, ~0x19)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_eround23",  F2(2, 0x19)|OPF_LOW4(1), F2(~2, ~0x19)|OPF_LOW4(~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround01",  F2(2, 0x19)|OPF_LOW4(2), F2(~2, ~0x19)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround23",  F2(2, 0x19)|OPF_LOW4(3), F2(~2, ~0x19)|OPF_LOW4(~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_eround01_l",F2(2, 0x19)|OPF_LOW4(4), F2(~2, ~0x19)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_eround23_l",F2(2, 0x19)|OPF_LOW4(5), F2(~2, ~0x19)|OPF_LOW4(~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround01_l",F2(2, 0x19)|OPF_LOW4(6), F2(~2, ~0x19)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround23_l",F2(2, 0x19)|OPF_LOW4(7), F2(~2, ~0x19)|OPF_LOW4(~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_kexpand1",  F2(2, 0x19)|OPF_LOW4(8), F2(~2, ~0x19)|OPF_LOW4(~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
-{"des_round",     F2(2, 0x19)|OPF_LOW4(9), F2(~2, ~0x19)|OPF_LOW4(~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
-{"kasumi_fl_xor", F2(2, 0x19)|OPF_LOW4(10), F2(~2, ~0x19)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
-{"kasumi_fi_xor", F2(2, 0x19)|OPF_LOW4(11), F2(~2, ~0x19)|OPF_LOW4(~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
-{"camellia_f",    F2(2, 0x19)|OPF_LOW4(12), F2(~2, ~0x19)|OPF_LOW4(~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
+{"aes_eround01",  F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_eround23",  F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround01",  F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround23",  F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_kexpand1",  F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
+{"des_round",     F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
+{"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
+{"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
+{"camellia_f",    F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
 { "flcmps",    CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
 { "flcmps",    CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
 { "flcmps",    CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },