]> git.ipfire.org Git - people/arne_f/kernel.git/commitdiff
powerpc: clean inclusions of asm/feature-fixups.h
authorChristophe Leroy <christophe.leroy@c-s.fr>
Thu, 5 Jul 2018 16:25:01 +0000 (16:25 +0000)
committerMichael Ellerman <mpe@ellerman.id.au>
Mon, 30 Jul 2018 12:48:17 +0000 (22:48 +1000)
files not using feature fixup don't need asm/feature-fixups.h
files using feature fixup need asm/feature-fixups.h

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
49 files changed:
arch/powerpc/include/asm/cputable.h
arch/powerpc/include/asm/dbell.h
arch/powerpc/include/asm/dt_cpu_ftrs.h
arch/powerpc/include/asm/exception-64s.h
arch/powerpc/include/asm/firmware.h
arch/powerpc/include/asm/kvm_booke_hv_asm.h
arch/powerpc/include/asm/mmu.h
arch/powerpc/include/asm/ppc_asm.h
arch/powerpc/include/asm/reg.h
arch/powerpc/kernel/cpu_setup_6xx.S
arch/powerpc/kernel/entry_32.S
arch/powerpc/kernel/entry_64.S
arch/powerpc/kernel/exceptions-64e.S
arch/powerpc/kernel/exceptions-64s.S
arch/powerpc/kernel/fpu.S
arch/powerpc/kernel/head_32.S
arch/powerpc/kernel/head_64.S
arch/powerpc/kernel/head_fsl_booke.S
arch/powerpc/kernel/idle_6xx.S
arch/powerpc/kernel/idle_book3s.S
arch/powerpc/kernel/idle_e500.S
arch/powerpc/kernel/idle_power4.S
arch/powerpc/kernel/l2cr_6xx.S
arch/powerpc/kernel/misc_32.S
arch/powerpc/kernel/misc_64.S
arch/powerpc/kernel/setup_32.c
arch/powerpc/kernel/setup_64.c
arch/powerpc/kernel/swsusp_32.S
arch/powerpc/kernel/swsusp_asm64.S
arch/powerpc/kernel/tm.S
arch/powerpc/kvm/book3s_64_slb.S
arch/powerpc/kvm/book3s_hv_interrupts.S
arch/powerpc/kvm/book3s_hv_rmhandlers.S
arch/powerpc/kvm/book3s_segment.S
arch/powerpc/lib/copypage_64.S
arch/powerpc/lib/copyuser_64.S
arch/powerpc/lib/hweight_64.S
arch/powerpc/lib/memcpy_64.S
arch/powerpc/mm/hash_low_32.S
arch/powerpc/mm/hash_native_64.c
arch/powerpc/mm/slb_low.S
arch/powerpc/mm/tlb_low_64e.S
arch/powerpc/mm/tlb_nohash_low.S
arch/powerpc/platforms/powermac/cache.S
arch/powerpc/platforms/powermac/sleep.S
arch/powerpc/platforms/powernv/opal-wrappers.S
arch/powerpc/platforms/pseries/hvCall.S
tools/testing/selftests/powerpc/copyloops/asm/feature-fixups.h [new file with mode: 0644]
tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h [new symlink]

index 751126c22ed950623702030e9dfb465224e1da43..29f49a35d6eecee903ee04ccf3732fadc2971070 100644 (file)
@@ -4,7 +4,6 @@
 
 
 #include <linux/types.h>
-#include <asm/feature-fixups.h>
 #include <uapi/asm/cputable.h>
 #include <asm/asm-const.h>
 
index 998c42ff1caab0c2ac44c503645c49ad7295d304..99b84db23e8c361e0f78faa33470f29fe46d9958 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/threads.h>
 
 #include <asm/ppc-opcode.h>
+#include <asm/feature-fixups.h>
 
 #define PPC_DBELL_MSG_BRDCAST  (0x04000000)
 #define PPC_DBELL_TYPE(x)      (((x) & 0xf) << (63-36))
index 55113432fc917f0640a60f7e303f257064018f93..0c729e2d0e8a1b555fb2898764848245f432ccfc 100644 (file)
@@ -10,7 +10,6 @@
  */
 
 #include <linux/types.h>
-#include <asm/feature-fixups.h>
 #include <uapi/asm/cputable.h>
 
 #ifdef CONFIG_PPC_DT_CPU_FTRS
index c40b4380951cb45518656a0e1030280d9253d852..1f2efc1a9769aae07a0f4523328f7479caff5d71 100644 (file)
@@ -35,6 +35,7 @@
  * implementations as possible.
  */
 #include <asm/head-64.h>
+#include <asm/feature-fixups.h>
 
 /* PACA save area offsets (exgen, exmc, etc) */
 #define EX_R9          0
index ce8aab72c21bb3225f922a4fa1cd79069fd4ad26..7a051bd21f87912272f190eec30a50ae2d9e0d52 100644 (file)
@@ -14,7 +14,6 @@
 
 #ifdef __KERNEL__
 
-#include <asm/feature-fixups.h>
 #include <asm/asm-const.h>
 
 /* firmware feature bitmask values */
index e5f048bbcb7c43569a0b0d9e8155b1f2732d4839..931260b59ac6563e0f73f74a470b4a900b6f569a 100644 (file)
@@ -9,6 +9,8 @@
 #ifndef ASM_KVM_BOOKE_HV_ASM_H
 #define ASM_KVM_BOOKE_HV_ASM_H
 
+#include <asm/feature-fixups.h>
+
 #ifdef __ASSEMBLY__
 
 /*
index 8418d83b5eb00dbfa6188d7d06df0d4a678e00c0..13ea441ac5319e27e1466362fde8f700d0b8f231 100644 (file)
@@ -5,7 +5,6 @@
 
 #include <linux/types.h>
 
-#include <asm/feature-fixups.h>
 #include <asm/asm-const.h>
 
 /*
index 75ece56dcd62580cc2761c3da1760fc2e4efc941..b5d023680801b982cb5af2d82a21e943a7af57b9 100644 (file)
@@ -9,6 +9,7 @@
 #include <asm/processor.h>
 #include <asm/ppc-opcode.h>
 #include <asm/firmware.h>
+#include <asm/feature-fixups.h>
 
 #ifdef __ASSEMBLY__
 
index d4a8dc71a0572af4460b149666e77abe6866930c..486b7c83b8c51975f64dde4077b23732d1600995 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/stringify.h>
 #include <asm/cputable.h>
 #include <asm/asm-const.h>
+#include <asm/feature-fixups.h>
 
 /* Pickup Book E specific registers. */
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
index a9f3970693e1b6b18a509beb0be537694971b382..fa3c2c91290cb4101b610165da980401b6de7c7b 100644 (file)
@@ -16,6 +16,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include <asm/feature-fixups.h>
 
 _GLOBAL(__setup_cpu_603)
        mflr    r5
index 7642cb984d3a119cb4f95142d0e30155283ab3eb..3bd097be90d929f91f1aaaebe19b9115e2a4047d 100644 (file)
@@ -34,6 +34,7 @@
 #include <asm/ptrace.h>
 #include <asm/export.h>
 #include <asm/asm-405.h>
+#include <asm/feature-fixups.h>
 
 /*
  * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
index f62d9ddc03122988f0cf6463b8b98d4f285d18fa..a9e74ecdab0b9e0a8bd47ceb1227433258dbf806 100644 (file)
@@ -44,6 +44,7 @@
 #else
 #include <asm/exception-64e.h>
 #endif
+#include <asm/feature-fixups.h>
 
 /*
  * System calls.
index 3325f721e7b251c17fb5a10645e1fb31f8d8417c..6d6e144a28ce0971d3be09d112d8b0404d57cb0f 100644 (file)
@@ -27,6 +27,7 @@
 #include <asm/hw_irq.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_booke_hv_asm.h>
+#include <asm/feature-fixups.h>
 
 /* XXX This will ultimately add space for a special exception save
  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
index 36aec1f1cb2d8c4c408977c89cf2d980c457cdec..7a672dafd94f5f169a5322ad99686c890fe1ce6a 100644 (file)
@@ -18,6 +18,7 @@
 #include <asm/ptrace.h>
 #include <asm/cpuidle.h>
 #include <asm/head-64.h>
+#include <asm/feature-fixups.h>
 
 /*
  * There are a few constraints to be concerned with.
index 07c913fd5abad8af733095c0e4d46a0da5ca77f2..529dcc21c3f91bd2646f9519d95edb7664b9e7f8 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/ptrace.h>
 #include <asm/export.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 #ifdef CONFIG_VSX
 #define __REST_32FPVSRS(n,c,base)                                      \
index 29b2fed9328973952bee3745982fcaf603bf09f5..61ca27929355a0eea397d22bff1792dc1d5f0c59 100644 (file)
@@ -35,6 +35,7 @@
 #include <asm/bug.h>
 #include <asm/kvm_book3s_asm.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
 #define LOAD_BAT(n, reg, RA, RB)       \
index 6eca15f25c730bf6b02413a08024837184c8c296..4898e9491a1cd3ab5b90b2e50c75758b7ebb9d00 100644 (file)
@@ -44,6 +44,7 @@
 #include <asm/cputhreads.h>
 #include <asm/ppc-opcode.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
 /* The physical memory is laid out such that the secondary processor
  * spin code sits at 0x0000...0x00ff. On server, the vectors follow
index bf4c6021515f8aedff5a8c2cfc39f37b39850982..e2750b856c8fc5468ca5065adb8be0ce88c5b18c 100644 (file)
@@ -43,6 +43,7 @@
 #include <asm/cache.h>
 #include <asm/ptrace.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 #include "head_booke.h"
 
 /* As with the other PowerPC ports, it is expected that when code
index 1686916cc7f0739dab7a0593e71e878c51f00b67..ff026c9d3cab42c3812d33fdc7d23cfbc5d1406b 100644 (file)
@@ -20,6 +20,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/feature-fixups.h>
 
        .text
 
index 436caa9d6eec8c6f8e516acec2be1253c9f33b5f..b107e3df7f8f67352352b139985f5322bad502fe 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/book3s/64/mmu-hash.h>
 #include <asm/mmu.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 #undef DEBUG
 
index b9b6ef510be1ec366576a718423b6c319e8e4c06..583e55ac7d26319ab38205d801211625a5809dbd 100644 (file)
@@ -17,6 +17,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/feature-fixups.h>
 
        .text
 
index 08faa93755f9f912bd9673be5bfa9ea363880aa4..dd7471fe20bd4960e3a8db2cd34deb64fde061b2 100644 (file)
@@ -16,6 +16,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/irqflags.h>
 #include <asm/hw_irq.h>
+#include <asm/feature-fixups.h>
 
 #undef DEBUG
 
index 6408f09dbbd9dc504d62da7b11ef65fbd18ac77c..6e7dbb7d527c8500b6810199af8924b311e54a25 100644 (file)
@@ -45,6 +45,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/cache.h>
 #include <asm/page.h>
+#include <asm/feature-fixups.h>
 
 /* Usage:
 
index 3f7a9a2d24356bef720d0b0660b78aa53f125884..695b24a2d9542fc2f0ed710a5ac5dffdb7ffdccd 100644 (file)
@@ -34,6 +34,7 @@
 #include <asm/bug.h>
 #include <asm/ptrace.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
        .text
 
index fa267e94090ac29080b6af8ad32906acd1a3787f..262ba948178107a8180a7aff69603e226a248cec 100644 (file)
@@ -28,6 +28,7 @@
 #include <asm/ptrace.h>
 #include <asm/mmu.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
        .text
 
index ef747a5a30b9ccded506dcc547fcd15b91eaa51c..0e37433432808f69bf0d9af4bd1ff933ad13c598 100644 (file)
@@ -41,6 +41,7 @@
 #include <asm/cpu_has_feature.h>
 #include <asm/asm-prototypes.h>
 #include <asm/kdump.h>
+#include <asm/feature-fixups.h>
 
 #define DBG(fmt...)
 
index 225bc5f91049436277e7c45787d8a7370d6dac78..6a501b25dd85f9290c86c30fcdda409be1f2002d 100644 (file)
@@ -68,6 +68,7 @@
 #include <asm/opal.h>
 #include <asm/cputhreads.h>
 #include <asm/hw_irq.h>
+#include <asm/feature-fixups.h>
 
 #include "setup.h"
 
index 34b73a262709c1f9d478d2b24f832ddf14169f0d..7a919e9a3400bb9a41cc98b42875b1285e9f5f02 100644 (file)
@@ -7,6 +7,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/mmu.h>
+#include <asm/feature-fixups.h>
 
 /*
  * Structure for storing CPU registers on the save area.
index 82d8aae81c6adb86ddbd07125e96eb936a48cc10..f83bf6f72cb0e461af4780cba1825bf186b610a1 100644 (file)
@@ -13,6 +13,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/feature-fixups.h>
 
 /*
  * Structure for storing CPU registers on the save area.
index 6bb6f5123dcf2bff9b0ad2373f6e337cb1625d87..6bffbc5affe76ba7847ceb74b69e16cc53ac4178 100644 (file)
@@ -13,6 +13,7 @@
 #include <asm/reg.h>
 #include <asm/bug.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
 #ifdef CONFIG_VSX
 /* See fpu.S, this is borrowed from there */
index d293485c1a6002595434284bfbaebd92e49767ce..066c665dc86fbd81fa95f4c539e4904b673fc425 100644 (file)
@@ -18,6 +18,7 @@
  */
 
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 #define SHADOW_SLB_ENTRY_LEN   0x10
 #define OFFSET_ESID(x)         (SHADOW_SLB_ENTRY_LEN * x)
index 4218073eea1fc81b0ac20db89e1bb3ecd69f430f..666b91c79eb41be0c582c4a08abdee8291c9aa09 100644 (file)
@@ -28,6 +28,7 @@
 #include <asm/exception-64s.h>
 #include <asm/ppc-opcode.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 /*****************************************************************************
  *                                                                           *
index 7405222a4e28a86b1724dd0ae23c56fe14288d12..1d14046124a01afffda02a70d73e7666b7b4b6bc 100644 (file)
@@ -33,6 +33,7 @@
 #include <asm/xive-regs.h>
 #include <asm/thread_info.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 /* Sign-extend HDEC if not on POWER9 */
 #define EXTEND_HDEC(reg)                       \
index 7fec258bb0725608f189943e60900b835925b5bd..e5c542a7c5aca41c5969ffe0e3cf27f5c17e2b97 100644 (file)
@@ -20,6 +20,7 @@
 /* Real mode helpers */
 
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 #if defined(CONFIG_PPC_BOOK3S_64)
 
index 8d5034f645f3ff599942e44a8740708c70dcf40b..694390357667312151f508e556aba713ff8d2455 100644 (file)
@@ -11,6 +11,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
         .section        ".toc","aw"
 PPC64_CACHES:
index 65244263b6a34971da3fdd9bf7af92b1e2680881..2d6f128d3ebe9e77be87f4e09347267508bcf4ad 100644 (file)
@@ -10,6 +10,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/export.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 #ifdef __BIG_ENDIAN__
 #define sLd sld                /* Shift towards low-numbered address. */
index 3de7ac154f24e7c1198ffdfc6942ff011088162f..0526b22252603fa7af97f81779de40e5c12bf1a5 100644 (file)
@@ -20,6 +20,7 @@
 #include <asm/processor.h>
 #include <asm/ppc_asm.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
 /* Note: This code relies on -mminimal-toc */
 
index 26ea02b7311fd0c1560825d4584027af63948c95..94650d6eae9cbd72669fb17afea140fad2ccf0cf 100644 (file)
@@ -10,6 +10,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/export.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
        .align  7
 _GLOBAL_TOC(memcpy)
index ffbd7c0bda968b1306bbafcac4703d2ae4ed0b61..26acf6c8c20c5b10c6ca428d06aafddbf8775472 100644 (file)
@@ -27,6 +27,7 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 #include <asm/export.h>
+#include <asm/feature-fixups.h>
 
 #ifdef CONFIG_SMP
        .section .bss
index ffbd5ed4e8de94886c33b7661e76341d8a213d46..fc5dbbfd09fec146d75d226b254f53e2bc3f2f3b 100644 (file)
@@ -30,6 +30,7 @@
 #include <asm/udbg.h>
 #include <asm/kexec.h>
 #include <asm/ppc-opcode.h>
+#include <asm/feature-fixups.h>
 
 #include <misc/cxl-base.h>
 
index a83fbd2a4a245dadeb9840b5480d85cff5fa6e26..4ac5057ad4393f07f9cb2aa9809582eb644f5b93 100644 (file)
@@ -22,6 +22,7 @@
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/firmware.h>
+#include <asm/feature-fixups.h>
 
 /*
  * This macro generates asm code to compute the VSID scramble
index eb82d787d99a1140e660b4e5675a241ee2b92a5c..7fd20c52a8ec8e2c5762bf5569cc9dd4def83724 100644 (file)
@@ -22,6 +22,7 @@
 #include <asm/ppc-opcode.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_booke_hv_asm.h>
+#include <asm/feature-fixups.h>
 
 #ifdef CONFIG_PPC_64K_PAGES
 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
index 505a3d010c479561f3d10cc8c2a3b02ef2cd1288..e066a658acac6f17872bf146fd884ef93e1f1723 100644 (file)
@@ -35,6 +35,7 @@
 #include <asm/processor.h>
 #include <asm/bug.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
 #if defined(CONFIG_40x)
 
index cc5347eb1662281fb7796b41c9ec78373135da2b..27862feee4a57b1a39ff2381aaa82b389ecdda8b 100644 (file)
@@ -17,6 +17,7 @@
 #include <asm/processor.h>
 #include <asm/ppc_asm.h>
 #include <asm/cputable.h>
+#include <asm/feature-fixups.h>
 
 /*
  * Flush and disable all data caches (dL1, L2, L3). This is used
index 1c2802fabd573f72a98fe2eb5c2540e12643c6a8..f89808b9713d0671d51d7a38ac0e8ae320b4d575 100644 (file)
@@ -18,6 +18,7 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 #include <asm/mmu.h>
+#include <asm/feature-fixups.h>
 
 #define MAGIC  0x4c617273      /* 'Lars' */
 
index 4016e3c3d18b4de00891a9944277089534169a1b..3508be7d758a64cd7634d0502240a4de9479fb81 100644 (file)
@@ -15,6 +15,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/opal.h>
 #include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
 
        .section        ".text"
 
index c511a1743a449aa6e0da5932c411f595708322b0..d91412c591effa968b7235f43bcf9081df07b4c6 100644 (file)
@@ -13,6 +13,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/ptrace.h>
+#include <asm/feature-fixups.h>
 
        .section        ".text"
        
diff --git a/tools/testing/selftests/powerpc/copyloops/asm/feature-fixups.h b/tools/testing/selftests/powerpc/copyloops/asm/feature-fixups.h
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h b/tools/testing/selftests/powerpc/primitives/asm/feature-fixups.h
new file mode 120000 (symlink)
index 0000000..8dc6d4d
--- /dev/null
@@ -0,0 +1 @@
+../../../../../../arch/powerpc/include/asm/feature-fixups.h
\ No newline at end of file