PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'

The 'link_gen' field is now holding the maximum supported link speed set
either by the controller driver or by DT through 'max-link-speed'
property.

However, the name 'link_gen' sounds like the negotiated link speed of
the PCIe link.

So rename it to 'max_link_speed' to make it clear that it holds the
maximum supported link speed of the controller.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-1-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 964d67756eb2be9847576d9a28fa087bf3457330..ef12a4f31740bf83d374076a38e25543fd119cc4 100644 (file)
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -847,12 +847,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
        if (ret)
                goto err_reset_phy;
 
-       if (pci->link_gen > 1) {
+       if (pci->max_link_speed > 1) {
                /* Allow faster modes after the link is up */
                dw_pcie_dbi_ro_wr_en(pci);
                tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
                tmp &= ~PCI_EXP_LNKCAP_SLS;
-               tmp |= pci->link_gen;
+               tmp |= pci->max_link_speed;
                dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
 
                /*
@@ -1386,8 +1386,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
                imx6_pcie->tx_swing_low = 127;
 
        /* Limit link speed */
-       pci->link_gen = 1;
-       of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
+       pci->max_link_speed = 1;
+       of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
 
        imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
        if (IS_ERR(imx6_pcie->vpcie)) {

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index bc3a5d6b017797f1d37a77f8b182020d2335d2b5..95ae6c65b28f1ba5188c0511f80bc9d50b5f8331 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -168,8 +168,8 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
                        return ret;
        }
 
-       if (pci->link_gen < 1)
-               pci->link_gen = of_pci_get_max_link_speed(np);
+       if (pci->max_link_speed < 1)
+               pci->max_link_speed = of_pci_get_max_link_speed(np);
 
        of_property_read_u32(np, "num-lanes", &pci->num_lanes);
 
@@ -689,7 +689,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
 
-static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
+static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 max_link_speed)
 {
        u32 cap, ctrl2, link_speed;
        u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -698,7 +698,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
        ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
        ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
 
-       switch (pcie_link_speed[link_gen]) {
+       switch (pcie_link_speed[max_link_speed]) {
        case PCIE_SPEED_2_5GT:
                link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
                break;
@@ -1060,8 +1060,8 @@ void dw_pcie_setup(struct dw_pcie *pci)
 {
        u32 val;
 
-       if (pci->link_gen > 0)
-               dw_pcie_link_set_max_speed(pci, pci->link_gen);
+       if (pci->max_link_speed > 0)
+               dw_pcie_link_set_max_speed(pci, pci->max_link_speed);
 
        /* Configure Gen1 N_FTS */
        if (pci->n_fts[0]) {

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index e518f81ea80cdaae1e54953742f6c725cdc6dc57..1a1769244e833d8e08c2813ffd182452b7a298c9 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -423,7 +423,7 @@ struct dw_pcie {
        u32                     type;
        unsigned long           caps;
        int                     num_lanes;
-       int                     link_gen;
+       int                     max_link_speed;
        u8                      n_fts[2];
        struct dw_edma_chip     edma;
        struct clk_bulk_data    app_clks[DW_PCIE_NUM_APP_CLKS];

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index acbe4f6d3291d829636093746fa2c339668334b9..676d2aba4fbdece16fc994f42e841ce701615ce1 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -132,7 +132,7 @@ static void intel_pcie_link_setup(struct intel_pcie *pcie)
 
 static void intel_pcie_init_n_fts(struct dw_pcie *pci)
 {
-       switch (pci->link_gen) {
+       switch (pci->max_link_speed) {
        case 3:
                pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;
                break;
@@ -252,7 +252,7 @@ static int intel_pcie_wait_l2(struct intel_pcie *pcie)
        int ret;
        struct dw_pcie *pci = &pcie->pci;
 
-       if (pci->link_gen < 3)
+       if (pci->max_link_speed < 3)
                return 0;
 
        /* Send PME_TURN_OFF message */

diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index f0f3ebd1a033eb388deb7344794caf2d2e3a6d98..00ad4832f2cf34e023370a49628120635ccefae3 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -141,10 +141,10 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
        }
 
        /*
-        * Require direct speed change with retrying here if the link_gen is
-        * PCIe Gen2 or higher.
+        * Require direct speed change with retrying here if the max_link_speed
+        * is PCIe Gen2 or higher.
         */
-       changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
+       changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1;
 
        /*
         * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.

diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
index 201dced209f0822fcd7faebbca2a7686bf016c8d..ff986ced56b2eede7b0b7c6643912482d02f6c04 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -233,7 +233,7 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
        }
 
        if (of_property_read_bool(np, "st,pcie-is-gen1"))
-               pci->link_gen = 1;
+               pci->max_link_speed = 1;
 
        platform_set_drvdata(pdev, spear13xx_pcie);