riscv: RISCV backend, meet C++20

C++20, in particular https://wg21.link/P1120R0 paper voted into it,
deprecates various operations between enumerators from different enumeration
types etc., and as we've switched to -std=gnu++20 by default, this now
results in warnings or errors during stage2 and onwards.

The following patch should fix riscv build.

2025-11-28  Jakub Jelinek  <jakub@redhat.com>

	* config/riscv/riscv-v.cc (expand_const_vector_onestep): Avoid
	bitwise ops between enumerators from different enum types.
	(emit_vec_cvt_x_f): Likewise.
	(emit_vec_cvt_x_f_rtz): Likewise.
	* config/riscv/riscv.cc (riscv_unspec_address_offset): Avoid
	arithmetics between enumerators from different enum types.

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c6c22371d9a98e41b553cfa444a71a8eb04e95f4..5e30b77b4ebf0d1156255b43b91af9b526e021ae 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1811,7 +1811,8 @@ expand_const_vector_onestep (rtx target, rvv_builder &builder)
   rtx dest = gen_reg_rtx (mode);
   insn_code icode = code_for_pred_mov (mode);
   rtx ops3[] = {dest, tmp3, tmp1};
-  emit_nonvlmax_insn (icode, __MASK_OP_TUMA | UNARY_OP_P, ops3, GEN_INT (n));
+  emit_nonvlmax_insn (icode, (unsigned) __MASK_OP_TUMA | UNARY_OP_P,
+                     ops3, GEN_INT (n));
 
   emit_move_insn (target, dest);
 }
@@ -5265,7 +5266,7 @@ emit_vec_cvt_x_f (rtx op_dest, rtx op_src, rtx mask,
 {
   insn_code icode = code_for_pred_fcvt_x_f (UNSPEC_VFCVT, vec_mode);
 
-  if (type & USE_VUNDEF_MERGE_P)
+  if (type & (insn_type) USE_VUNDEF_MERGE_P)
     {
       rtx cvt_x_ops[] = {op_dest, mask, op_src};
       emit_vlmax_insn (icode, type, cvt_x_ops);
@@ -5333,7 +5334,7 @@ emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask,
 {
   insn_code icode = code_for_pred (FIX, vec_mode);
 
-  if (type & USE_VUNDEF_MERGE_P)
+  if (type & (insn_type) USE_VUNDEF_MERGE_P)
     {
       rtx cvt_x_ops[] = {op_dest, mask, op_src};
       emit_vlmax_insn (icode, type, cvt_x_ops);

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3e737d54d57f68cf57758eafad38b40be101b56a..1804d5a689b4f88a7bf08bca2263d5e1117c20ee 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2864,7 +2864,7 @@ riscv_unspec_address_offset (rtx base, rtx offset,
                             enum riscv_symbol_type symbol_type)
 {
   base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
-                        UNSPEC_ADDRESS_FIRST + symbol_type);
+                        UNSPEC_ADDRESS_FIRST + (int) symbol_type);
   if (offset != const0_rtx)
     base = gen_rtx_PLUS (Pmode, base, offset);
   return gen_rtx_CONST (Pmode, base);