mtd: spi-nor: get rid of SPI_NOR_NO_FR

The Everspin FRAM devices are the only user of the NO_FR flag. Drop the
global flag and instead use a manufacturer fixup for the Everspin
flashes to drop the fast read support.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
[pratyush@kernel.org: s/evervision/everspin/g in code and commit message]
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
Link: https://lore.kernel.org/r/20240419141249.609534-5-mwalle@kernel.org

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 52e95c489544a3dc6bd79415ba321f2c19e2d71b..7128d45870d49fd37cb3d15419201084f7197cb3 100644 (file)
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2923,15 +2923,10 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
        params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;
        params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS;
 
-       if (!(info->flags & SPI_NOR_NO_FR)) {
-               /* Default to Fast Read for DT and non-DT platform devices. */
+       /* Default to Fast Read for non-DT and enable it if requested by DT. */
+       if (!np || of_property_read_bool(np, "m25p,fast-read"))
                params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
 
-               /* Mask out Fast Read if not requested at DT instantiation. */
-               if (np && !of_property_read_bool(np, "m25p,fast-read"))
-                       params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
-       }
-
        /* (Fast) Read settings. */
        params->hwcaps.mask |= SNOR_HWCAPS_READ;
        spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],

diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 497957b6490665bec5f135f08e46687aef916c27..1516b6d0dc37a3dc7cec3a92e18dd5b9911aac11 100644 (file)
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -470,7 +470,6 @@ struct spi_nor_id {
  *                            Usually these will power-up in a write-protected
  *                            state.
  *   SPI_NOR_NO_ERASE:        no erase command needed.
- *   SPI_NOR_NO_FR:           can't do fastread.
  *   SPI_NOR_QUAD_PP:         flash supports Quad Input Page Program.
  *   SPI_NOR_RWW:             flash supports reads while write.
  *
@@ -519,7 +518,6 @@ struct flash_info {
 #define SPI_NOR_BP3_SR_BIT6            BIT(4)
 #define SPI_NOR_SWP_IS_VOLATILE                BIT(5)
 #define SPI_NOR_NO_ERASE               BIT(6)
-#define SPI_NOR_NO_FR                  BIT(7)
 #define SPI_NOR_QUAD_PP                        BIT(8)
 #define SPI_NOR_RWW                    BIT(9)
 

diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index 5f321e24ae7d44ed6946dba0e738918f202270ab..add37104d6736851c3e408b1e29574821e1be4e3 100644 (file)
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -14,28 +14,39 @@ static const struct flash_info everspin_nor_parts[] = {
                .size = SZ_16K,
                .sector_size = SZ_16K,
                .addr_nbytes = 2,
-               .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
+               .flags = SPI_NOR_NO_ERASE,
        }, {
                .name = "mr25h256",
                .size = SZ_32K,
                .sector_size = SZ_32K,
                .addr_nbytes = 2,
-               .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
+               .flags = SPI_NOR_NO_ERASE,
        }, {
                .name = "mr25h10",
                .size = SZ_128K,
                .sector_size = SZ_128K,
-               .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
+               .flags = SPI_NOR_NO_ERASE,
        }, {
                .name = "mr25h40",
                .size = SZ_512K,
                .sector_size = SZ_512K,
-               .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
+               .flags = SPI_NOR_NO_ERASE,
        }
 };
 
+static void everspin_nor_default_init(struct spi_nor *nor)
+{
+       /* Everspin FRAMs don't support the fast read opcode. */
+       nor->params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
+}
+
+static const struct spi_nor_fixups everspin_nor_fixups = {
+       .default_init = everspin_nor_default_init,
+};
+
 const struct spi_nor_manufacturer spi_nor_everspin = {
        .name = "everspin",
        .parts = everspin_nor_parts,
        .nparts = ARRAY_SIZE(everspin_nor_parts),
+       .fixups = &everspin_nor_fixups,
 };