target_ulong addr, mask, pagesize;
uint8_t tlb_ps;
LoongArchTLB *tlb = &env->tlb[index];
-
- int mmu_idx = cpu_mmu_index(env_cpu(env), false);
+ int idxmap = BIT(MMU_KERNEL_IDX) | BIT(MMU_USER_IDX);
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
if (tlb_v0) {
tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
- mmu_idx, TARGET_LONG_BITS);
+ idxmap, TARGET_LONG_BITS);
}
if (tlb_v1) {
tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize,
- mmu_idx, TARGET_LONG_BITS);
+ idxmap, TARGET_LONG_BITS);
}
}