RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15

Add asm dump check test for vec_duplicate + vor.vv combine to vor.vx,
with the GR2VR cost is 0, 2 and 15.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add test cases
	for vor vx combine case 0 on GR2VR cost.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for vor.vx run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index ad63a84c93500034f0b7082c7b1a1e6c38620031..b15cb4cb8e6f6ae3c49841d7990fdcaf5b15a8d3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 87d7ecbb3febbbd98333f214f3d0e3ca5a613736..df3d3a33a34221a004d7e17b2b6aba624a93a31d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 4a402e5fe2cd39e734b4ca6fb4e34d35075d9dc5..ed17b83157769a46d1e01345554f5319e55ce79e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index b30c539f3101967a2ab65d449ed90b864c9aa19a..aa11dafc677fec6d23db18f07a223dadb8dab942 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index fd3d726e7bd671ba4c481f0f802b9a54da7d565b..15db5887a035360d6fae181ef4cfd0cd896c1c78 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 917e370cdc69e3b72e393164e90c6fc2a2525861..f15592c40eb2e7df4f1ed3139fbe7a07d71cec5a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 976a1b4687c17359900faf529d795ad1a518b22e..80e32afe8435749a89f18e92bd8cdcf173d91019 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index e96df13820b2d6c8fa4f85c3ace3ce4805455ae4..9b19276f2e6b89d747200c850536c84c893b42d3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 4912dbf415e8ebcf19eb8104900d2df026d02ef4..596488c877030d5e63b6955bb687fae32caac1bc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 1219395bf3037e5c4134c5902c1f40e15a045a93..8b4b7ebd2897df831f5bb4d9b69842dade389ef7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 64604e228ee7c2a28da156efc64b10b589b39497..544c9074a15c3076685f8bdf78b4ef298e208cef 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index e6d5e633b7bb62aa127e057dae5fc121059d0b51..af53f2b9ca43b47c1d08957d0bdf5237abf2bb80 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 35bf020705df85e706ba3f3f959ce56685ba9dec..a8ff915d7073a07736e6ce6698785953b55e0404 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 2c9d857dcbf27a498a96b980d49ebed3c95a4c5d..d587a88463e10838da3fa465845d1c6cca4469e2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index ac49bffba63b2e31a61e6710707c593d02dba163..ff205d53a55fe2b809a48520814279494f1e09cb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 8a3d027a57e14255962a9410217ccb2be8de9b29..e8e2c7fb6e70453487792fb10b13676012964918 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index b57d4e41b3462279b726eb480d9dd0f7db85de0c..bd38b86bc552ad5a1624b68c56c2a6ee7d852ed4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 517fc0a3ed3af0261d037616887084a8be7d246e..e0bdd2259fac024faf6c2e226db55ae5c56ec1e4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 8ba77099f8596ce4fe42c01fc391d4a8edbb200d..aab3b4afc7ff10ebcb943780a830d7eb49b7bbb6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index e71127f45665d523bdf5122d82c2699028ba736d..825988b04ccea321c6789bd89a591f864211adbe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 82d96e9289b4af89b2b06a24dba20206f0e8a2f4..a750510c1cee969495f5cd4abde944e3a349b252 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index e19513ad18bd18c601c078d12d3f46e30fffecf3..2d279cfa478fcef00625c2b3c261c476d08c63d0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 62a47ec14b0017dae6f985f33009321827c3d92e..5a90883c1df4922b4fbde7d413e4764e1a5d6a0b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index d693c367c91f6bb619bcc95bd1900bdab7a8e1b6..69af97a3a994c292764317f22b6b1a1312c284e0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index a5b4f95473531dfffb3df56ff730ea930da9c5b3..cd3cede15c82fe8694d7a92cad58ee6b9747ab27 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1574,4 +1574,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, and)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x3,  0x3,  0x3,  0x3,
+       0x1,  0x1,  0x1,  0x1,
+      0xff, 0xff, 0xff, 0xff,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0xff, 0xff, 0xff, 0xff,
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x7f, 0x7f, 0x7f, 0x7f,
+    },
+  },
+  {
+    { 0xf0 },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0xff, 0xff, 0xff, 0xff,
+      0xf0, 0xf0, 0xf0, 0xf0,
+      0xf1, 0xf1, 0xf1, 0xf1,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x3,    0x3,    0x3,    0x3,
+         0x1,    0x1,    0x1,    0x1,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    },
+  },
+  {
+    { 0xfff0 },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0xfff0, 0xfff0, 0xfff0, 0xfff0,
+      0xfff1, 0xfff1, 0xfff1, 0xfff1,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x3,        0x3,        0x3,        0x3,
+             0x1,        0x1,        0x1,        0x1,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+    },
+  },
+  {
+    { 0xfffffff0 },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0,
+      0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x3,                   0x3,                   0x3,                   0x3,
+                        0x1,                   0x1,                   0x1,                   0x1,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+    },
+  },
+  {
+    { 0xfffffffffffffff0ull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull,
+      0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
+    },
+  },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x3,  0x3,  0x3,  0x3,
+       0x1,  0x1,  0x1,  0x1,
+      0xff, 0xff, 0xff, 0xff,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0xff, 0xff, 0xff, 0xff,
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x7f, 0x7f, 0x7f, 0x7f,
+    },
+  },
+  {
+    { 0xf0 },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0xff, 0xff, 0xff, 0xff,
+      0xf0, 0xf0, 0xf0, 0xf0,
+      0xf1, 0xf1, 0xf1, 0xf1,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x3,    0x3,    0x3,    0x3,
+         0x1,    0x1,    0x1,    0x1,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+    },
+  },
+  {
+    { 0xfff0 },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0xfff0, 0xfff0, 0xfff0, 0xfff0,
+      0xfff1, 0xfff1, 0xfff1, 0xfff1,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x3,        0x3,        0x3,        0x3,
+             0x1,        0x1,        0x1,        0x1,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+    },
+  },
+  {
+    { 0xfffffff0 },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0,
+      0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x3,                   0x3,                   0x3,                   0x3,
+                        0x1,                   0x1,                   0x1,                   0x1,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+    },
+  },
+  {
+    { 0xfffffffffffffff0ull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull,
+      0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c
new file mode 100644 (file)
index 0000000..0a11aad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c
new file mode 100644 (file)
index 0000000..759ad2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c
new file mode 100644 (file)
index 0000000..1b3007c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c
new file mode 100644 (file)
index 0000000..b060744
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c
new file mode 100644 (file)
index 0000000..0dc8bee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c
new file mode 100644 (file)
index 0000000..8bc2528
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint32_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c
new file mode 100644 (file)
index 0000000..d286bdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c
new file mode 100644 (file)
index 0000000..dba4338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"