clk: meson: meson8b: Export the video clocks

Setting the video clocks requires fine-tuned adjustments of various
video clocks. Export the required ones to allow changing the video clock
for the CVBS and HDMI outputs at runtime.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-7-martin.blumenstingl@googlemail.com

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index b1a5074cf148b60801e474e17e3d5b3bf95c6d32..c764143e2617fc7dc105c9c1293fc7470be7c763 100644 (file)
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -107,14 +107,11 @@
 #define CLKID_PERIPH_SEL       125
 #define CLKID_AXI_SEL          127
 #define CLKID_L2_DRAM_SEL      129
-#define CLKID_HDMI_PLL_LVDS_OUT        131
-#define CLKID_HDMI_PLL_HDMI_OUT        132
+#define CLKID_HDMI_PLL_LVDS_OUT 131
 #define CLKID_VID_PLL_IN_SEL   133
 #define CLKID_VID_PLL_IN_EN    134
 #define CLKID_VID_PLL_PRE_DIV  135
 #define CLKID_VID_PLL_POST_DIV 136
-#define CLKID_VID_PLL_FINAL_DIV        137
-#define CLKID_VCLK_IN_SEL      138
 #define CLKID_VCLK_IN_EN       139
 #define CLKID_VCLK_DIV1                140
 #define CLKID_VCLK_DIV2_DIV    141
@@ -125,7 +122,6 @@
 #define CLKID_VCLK_DIV6                146
 #define CLKID_VCLK_DIV12_DIV   147
 #define CLKID_VCLK_DIV12       148
-#define CLKID_VCLK2_IN_SEL     149
 #define CLKID_VCLK2_IN_EN      150
 #define CLKID_VCLK2_DIV1       151
 #define CLKID_VCLK2_DIV2_DIV   152
@@ -137,17 +133,11 @@
 #define CLKID_VCLK2_DIV12_DIV  158
 #define CLKID_VCLK2_DIV12      159
 #define CLKID_CTS_ENCT_SEL     160
-#define CLKID_CTS_ENCT         161
 #define CLKID_CTS_ENCP_SEL     162
-#define CLKID_CTS_ENCP         163
 #define CLKID_CTS_ENCI_SEL     164
-#define CLKID_CTS_ENCI         165
 #define CLKID_HDMI_TX_PIXEL_SEL        166
-#define CLKID_HDMI_TX_PIXEL    167
 #define CLKID_CTS_ENCL_SEL     168
-#define CLKID_CTS_ENCL         169
 #define CLKID_CTS_VDAC0_SEL    170
-#define CLKID_CTS_VDAC0                171
 #define CLKID_HDMI_SYS_SEL     172
 #define CLKID_HDMI_SYS_DIV     173
 #define CLKID_MALI_0_SEL       175

diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index f33781338eda7b088f022a5ec9c754c2d65c506c..78aa07fd7cc0ab8158e8ab915b64ff750b3ebfd2 100644 (file)
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -105,6 +105,16 @@
 #define CLKID_PERIPH           126
 #define CLKID_AXI              128
 #define CLKID_L2_DRAM          130
+#define CLKID_HDMI_PLL_HDMI_OUT        132
+#define CLKID_VID_PLL_FINAL_DIV        137
+#define CLKID_VCLK_IN_SEL      138
+#define CLKID_VCLK2_IN_SEL     149
+#define CLKID_CTS_ENCT         161
+#define CLKID_CTS_ENCP         163
+#define CLKID_CTS_ENCI         165
+#define CLKID_HDMI_TX_PIXEL    167
+#define CLKID_CTS_ENCL         169
+#define CLKID_CTS_VDAC0                171
 #define CLKID_HDMI_SYS         174
 #define CLKID_VPU              190
 #define CLKID_VDEC_1           196