drm/xe: Move LRC_ENGINE_ID_PPHWSP_OFFSET outside of parallel offset

The parallel scratch layout spans 2k and LRC_ENGINE_ID_PPHWSP_OFFSET
lands within than space. This happens to be ok as the offset lands in
reserved part of guc_sched_wq_desc, but for future safety move
LRC_ENGINE_ID_PPHWSP_OFFSET to the unused offset of 1024 below parallel
scratch layout.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://lore.kernel.org/r/20250612172850.4170428-1-matthew.brost@intel.com

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index a875b93697a5f7573d48e4907150a7d4d73119cd..37598588a54f6eb5d72d2a81ba88840ae21ac0d1 100644 (file)
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -655,8 +655,8 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
 #define LRC_SEQNO_PPHWSP_OFFSET 512
 #define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
 #define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
+#define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
 #define LRC_PARALLEL_PPHWSP_OFFSET 2048
-#define LRC_ENGINE_ID_PPHWSP_OFFSET 2096
 
 u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
 {