* cse.c (hash_rtx_cb): Replace RTX_UNCHANGING_P with MEM_READONLY_P in

	head comment.
	(hash_rtx): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@193001 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d4622cc06ad7e827ab688007e947e7c8c7241658..12b1504232a42a1a74324a187fe299f0c65caf83 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2012-10-30  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * cse.c (hash_rtx_cb): Replace RTX_UNCHANGING_P with MEM_READONLY_P in
+       head comment.
+       (hash_rtx): Likewise.
+
 2012-10-30  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR rtl-optimization/55093

diff --git a/gcc/cse.c b/gcc/cse.c
index c7a75eae45447aff8a8b4951756fb109e6c692ff..b41d47a36a2a2f2954fe8e5523999cad7627c46f 100644 (file)
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -2547,7 +2547,7 @@ hash_rtx_cb (const_rtx x, enum machine_mode mode,
    Store 1 in DO_NOT_RECORD_P if any subexpression is volatile.
 
    If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains
-   a MEM rtx which does not have the RTX_UNCHANGING_P bit set.
+   a MEM rtx which does not have the MEM_READONLY_P flag set.
 
    Note that cse_insn knows that the hash code of a MEM expression
    is just (int) MEM plus the hash code of the address.  */
@@ -2563,7 +2563,7 @@ hash_rtx (const_rtx x, enum machine_mode mode, int *do_not_record_p,
 /* Hash an rtx X for cse via hash_rtx.
    Stores 1 in do_not_record if any subexpression is volatile.
    Stores 1 in hash_arg_in_memory if X contains a mem rtx which
-   does not have the RTX_UNCHANGING_P bit set.  */
+   does not have the MEM_READONLY_P flag set.  */
 
 static inline unsigned
 canon_hash (rtx x, enum machine_mode mode)