27ad37728c3f wifi: mt76: mt7996: Check phy before init msta_link in mt7996_mac_sta_add_links()
95c9b8099ede wifi: mt76: mt7996: Set EML capabilities for AP interface
08df8dd7b00b wifi: mt76: mt7996: Use proper link_id in link_sta_rc_update callback
15fa4e33ee8f wifi: mt76: mt7996: Enable MLO support for client interfaces
3400b1ba33be wifi: mt76: mt7925: add pci restore for hibernate
51a1c0a086c8 wifi: mt76: mt7921: Add 160MHz beamformee capability for mt7922 device
435e596914fa wifi: mt76: mt7996: Use proper link info in mt7996_mcu_add_group
d30faac3b645 firmware: update mt7996 and mt7992 firmware to
20250606
304226bc4552 wifi: mt76: mt7996: Fix mt7996_reverse_frag0_hdr_trans for MLO
7cf18f8ebbb8 wifi: mt76: mt7996: Add all active links to poll list in mt7996_mac_tx_free()
16090cb27d9f wifi: mt76: mt7996: Implement MLD address translation for EAPOL
a1c319500a53 wifi: mt76: mt7996: Temporarily disable EPCS
5f3ea4562fbf wifi: mt76: mt7921: Place upper limit on station AID
ef2468830f6d wifi: mt76: un-embedd netdev from mt76_dev
29bca0ca462b net: mediatek: wed: Introduce MT7992 WED support to MT7988 SoC
245f6ff460c8 wifi: mt76: Add reset_idx to reset_q mt76_queue_ops signature.
4a3a5a7d71a8 wifi: mt76: Remove q->ndesc check in mt76_dma_rx_fill()
d540538299f7 wifi: mt76: Differentiate between RRO data and RRO MSDU queues
d0217732f96e wifi: mt76: Do not always enable NAPIs for WED RRO queues
1df790839241 wifi: mt76: mt7996: Initial DMA configuration for MT7992 WED support
fca511f401e9 wifi: mt76: mt7996: Enable HW RRO for MT7992 chipset
8134055d3459 wifi: mt76: mt7996: Introduce the capability to reset MT7992 WED device
4f81d751b5de wifi: mt76: mt7996: Fix tx-queues initialization for second phy on mt7996
f559eef156fd wifi: mt76: mt7996: Fix RX packets configuration for primary WED device
6b518355fec6 wifi: mt76: mt7996: Enable WED for MT7992 chipset
13eb05fa4a43 wifi: mt76: mt7996: Introduce RRO MSDU callbacks
ac1bca49973b wifi: mt76: Add rx_queue_init callback
d82330a9d019 wifi: mt76: mt7996: Decouple RRO logic from WED support
0a32ae3cc23d wifi: mt76: Add mt76_dma_get_rxdmad_c_buf utility routione
6c902ccba889 wifi: mt76: mt7996: Add SW path for HW-RRO v3.1
Signed-off-by: Felix Fietkau <nbd@nbd.name>
PKG_SOURCE_URL:=https://github.com/openwrt/mt76
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2025-08-27
-PKG_SOURCE_VERSION:=de1df8b888bd1c99ee191f451af47b4fa9658e8c
-PKG_MIRROR_HASH:=4ead68e97fc6472a682dae2f96f9dbb377f23c316511f625b85af15de46e9397
+PKG_SOURCE_DATE:=2025-09-04
+PKG_SOURCE_VERSION:=6c902ccba889a83b9f3d69bedf0cea0eebb621a4
+PKG_MIRROR_HASH:=c73e2ab638ccc995d833e9823a645a67ad76765ef981d5963aafb3faf25a92d5
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_USE_NINJA:=0
--- /dev/null
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 12 Aug 2025 06:57:23 +0200
+Subject: [PATCH] net: mediatek: wed: Introduce MT7992 WED support to MT7988
+ SoC
+
+Introduce the second WDMA RX ring in WED driver for MT7988 SoC since the
+Mediatek MT7992 WiFi chipset supports two separated WDMA rings.
+Add missing MT7988 configurations to properly support WED for MT7992 in
+MT76 driver.
+
+Co-developed-by: Rex Lu <rex.lu@mediatek.com>
+Signed-off-by: Rex Lu <rex.lu@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://patch.msgid.link/20250812-mt7992-wed-support-v3-1-9ada78a819a4@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -59,7 +59,9 @@ struct mtk_wed_flow_block_priv {
+ static const struct mtk_wed_soc_data mt7622_data = {
+ .regmap = {
+ .tx_bm_tkid = 0x088,
+- .wpdma_rx_ring0 = 0x770,
++ .wpdma_rx_ring = {
++ 0x770,
++ },
+ .reset_idx_tx_mask = GENMASK(3, 0),
+ .reset_idx_rx_mask = GENMASK(17, 16),
+ },
+@@ -70,7 +72,9 @@ static const struct mtk_wed_soc_data mt7
+ static const struct mtk_wed_soc_data mt7986_data = {
+ .regmap = {
+ .tx_bm_tkid = 0x0c8,
+- .wpdma_rx_ring0 = 0x770,
++ .wpdma_rx_ring = {
++ 0x770,
++ },
+ .reset_idx_tx_mask = GENMASK(1, 0),
+ .reset_idx_rx_mask = GENMASK(7, 6),
+ },
+@@ -81,7 +85,10 @@ static const struct mtk_wed_soc_data mt7
+ static const struct mtk_wed_soc_data mt7988_data = {
+ .regmap = {
+ .tx_bm_tkid = 0x0c8,
+- .wpdma_rx_ring0 = 0x7d0,
++ .wpdma_rx_ring = {
++ 0x7d0,
++ 0x7d8,
++ },
+ .reset_idx_tx_mask = GENMASK(1, 0),
+ .reset_idx_rx_mask = GENMASK(7, 6),
+ },
+@@ -621,8 +628,8 @@ mtk_wed_amsdu_init(struct mtk_wed_device
+ return ret;
+ }
+
+- /* eagle E1 PCIE1 tx ring 22 flow control issue */
+- if (dev->wlan.id == 0x7991)
++ /* Kite and Eagle E1 PCIE1 tx ring 22 flow control issue */
++ if (dev->wlan.id == 0x7991 || dev->wlan.id == 0x7992)
+ wed_clr(dev, MTK_WED_AMSDU_FIFO, MTK_WED_AMSDU_IS_PRIOR0_RING);
+
+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
+@@ -1239,7 +1246,11 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+ return;
+
+ wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
+- wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
++ wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[0],
++ dev->wlan.wpdma_rx[0]);
++ if (mtk_wed_is_v3_or_greater(dev->hw))
++ wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[1],
++ dev->wlan.wpdma_rx[1]);
+
+ if (!dev->wlan.hw_rro)
+ return;
+@@ -2335,6 +2346,16 @@ mtk_wed_start(struct mtk_wed_device *dev
+ if (!dev->rx_wdma[i].desc)
+ mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
+
++ if (dev->wlan.hw_rro) {
++ for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
++ u32 addr = MTK_WED_RRO_MSDU_PG_CTRL0(i) +
++ MTK_WED_RING_OFS_COUNT;
++
++ if (!wed_r32(dev, addr))
++ wed_w32(dev, addr, 1);
++ }
++ }
++
+ mtk_wed_hw_init(dev);
+ mtk_wed_configure_irq(dev, irq_mask);
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
+@@ -17,7 +17,7 @@ struct mtk_wed_wo;
+ struct mtk_wed_soc_data {
+ struct {
+ u32 tx_bm_tkid;
+- u32 wpdma_rx_ring0;
++ u32 wpdma_rx_ring[MTK_WED_RX_QUEUES];
+ u32 reset_idx_tx_mask;
+ u32 reset_idx_rx_mask;
+ } regmap;
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -147,7 +147,7 @@ struct mtk_wed_device {
+ u32 wpdma_tx;
+ u32 wpdma_txfree;
+ u32 wpdma_rx_glo;
+- u32 wpdma_rx;
++ u32 wpdma_rx[MTK_WED_RX_QUEUES];
+ u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
+ u32 wpdma_rx_pg;
+
--- /dev/null
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 12 Aug 2025 06:57:23 +0200
+Subject: [PATCH] net: mediatek: wed: Introduce MT7992 WED support to MT7988
+ SoC
+
+Introduce the second WDMA RX ring in WED driver for MT7988 SoC since the
+Mediatek MT7992 WiFi chipset supports two separated WDMA rings.
+Add missing MT7988 configurations to properly support WED for MT7992 in
+MT76 driver.
+
+Co-developed-by: Rex Lu <rex.lu@mediatek.com>
+Signed-off-by: Rex Lu <rex.lu@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://patch.msgid.link/20250812-mt7992-wed-support-v3-1-9ada78a819a4@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -59,7 +59,9 @@ struct mtk_wed_flow_block_priv {
+ static const struct mtk_wed_soc_data mt7622_data = {
+ .regmap = {
+ .tx_bm_tkid = 0x088,
+- .wpdma_rx_ring0 = 0x770,
++ .wpdma_rx_ring = {
++ 0x770,
++ },
+ .reset_idx_tx_mask = GENMASK(3, 0),
+ .reset_idx_rx_mask = GENMASK(17, 16),
+ },
+@@ -70,7 +72,9 @@ static const struct mtk_wed_soc_data mt7
+ static const struct mtk_wed_soc_data mt7986_data = {
+ .regmap = {
+ .tx_bm_tkid = 0x0c8,
+- .wpdma_rx_ring0 = 0x770,
++ .wpdma_rx_ring = {
++ 0x770,
++ },
+ .reset_idx_tx_mask = GENMASK(1, 0),
+ .reset_idx_rx_mask = GENMASK(7, 6),
+ },
+@@ -81,7 +85,10 @@ static const struct mtk_wed_soc_data mt7
+ static const struct mtk_wed_soc_data mt7988_data = {
+ .regmap = {
+ .tx_bm_tkid = 0x0c8,
+- .wpdma_rx_ring0 = 0x7d0,
++ .wpdma_rx_ring = {
++ 0x7d0,
++ 0x7d8,
++ },
+ .reset_idx_tx_mask = GENMASK(1, 0),
+ .reset_idx_rx_mask = GENMASK(7, 6),
+ },
+@@ -621,8 +628,8 @@ mtk_wed_amsdu_init(struct mtk_wed_device
+ return ret;
+ }
+
+- /* eagle E1 PCIE1 tx ring 22 flow control issue */
+- if (dev->wlan.id == 0x7991)
++ /* Kite and Eagle E1 PCIE1 tx ring 22 flow control issue */
++ if (dev->wlan.id == 0x7991 || dev->wlan.id == 0x7992)
+ wed_clr(dev, MTK_WED_AMSDU_FIFO, MTK_WED_AMSDU_IS_PRIOR0_RING);
+
+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
+@@ -1239,7 +1246,11 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+ return;
+
+ wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
+- wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
++ wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[0],
++ dev->wlan.wpdma_rx[0]);
++ if (mtk_wed_is_v3_or_greater(dev->hw))
++ wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[1],
++ dev->wlan.wpdma_rx[1]);
+
+ if (!dev->wlan.hw_rro)
+ return;
+@@ -2335,6 +2346,16 @@ mtk_wed_start(struct mtk_wed_device *dev
+ if (!dev->rx_wdma[i].desc)
+ mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
+
++ if (dev->wlan.hw_rro) {
++ for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
++ u32 addr = MTK_WED_RRO_MSDU_PG_CTRL0(i) +
++ MTK_WED_RING_OFS_COUNT;
++
++ if (!wed_r32(dev, addr))
++ wed_w32(dev, addr, 1);
++ }
++ }
++
+ mtk_wed_hw_init(dev);
+ mtk_wed_configure_irq(dev, irq_mask);
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
+@@ -17,7 +17,7 @@ struct mtk_wed_wo;
+ struct mtk_wed_soc_data {
+ struct {
+ u32 tx_bm_tkid;
+- u32 wpdma_rx_ring0;
++ u32 wpdma_rx_ring[MTK_WED_RX_QUEUES];
+ u32 reset_idx_tx_mask;
+ u32 reset_idx_rx_mask;
+ } regmap;
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -147,7 +147,7 @@ struct mtk_wed_device {
+ u32 wpdma_tx;
+ u32 wpdma_txfree;
+ u32 wpdma_rx_glo;
+- u32 wpdma_rx;
++ u32 wpdma_rx[MTK_WED_RX_QUEUES];
+ u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
+ u32 wpdma_rx_pg;
+
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1322,6 +1322,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1333,6 +1333,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
-@@ -1338,6 +1356,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1349,6 +1367,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;