--- /dev/null
+From 97ba26b8a9343008504d4e3a87d212bc07b05212 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 1 Apr 2017 15:59:21 +0200
+Subject: pinctrl: meson: meson8b: fix the NAND DQS pins
+
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+commit 97ba26b8a9343008504d4e3a87d212bc07b05212 upstream.
+
+The nand_groups table uses different names for the NAND DQS pins than
+the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0).
+This prevents using the NAND DQS pins in the devicetree.
+
+Fix this by ensuring that the GROUP() definition and the
+meson8b_cbus_groups use the same name for these pins.
+
+Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Acked-by: Kevin Hilman <khilman@baylibre.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/meson/pinctrl-meson8b.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
++++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
+@@ -732,8 +732,8 @@ static const char * const sdxc_c_groups[
+ static const char * const nand_groups[] = {
+ "nand_io", "nand_io_ce0", "nand_io_ce1",
+ "nand_io_rb0", "nand_ale", "nand_cle",
+- "nand_wen_clk", "nand_ren_clk", "nand_dqs0",
+- "nand_dqs1"
++ "nand_wen_clk", "nand_ren_clk", "nand_dqs_0",
++ "nand_dqs_1"
+ };
+
+ static const char * const nor_groups[] = {
--- /dev/null
+From da6c2addf66d7ff7d0b090d6267d4292f951e4e6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Thu, 18 May 2017 11:23:55 +0200
+Subject: pinctrl: mxs: atomically switch mux and drive strength config
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+commit da6c2addf66d7ff7d0b090d6267d4292f951e4e6 upstream.
+
+To set the mux mode of a pin two bits must be set. Up to now this is
+implemented using the following idiom:
+
+ writel(mask, reg + CLR);
+ writel(value, reg + SET);
+
+. This however results in the mux mode being 0 between the two writes.
+
+On my machine there is an IC's reset pin connected to LCD_D20. The
+bootloader configures this pin as GPIO output-high (i.e. not holding the
+IC in reset). When Linux reconfigures the pin to GPIO the short time
+LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
+the connected IC.
+
+The same problem is present for the pin's drive strength setting which is
+reset to low drive strength before using the right value.
+
+So instead of relying on the hardware to modify the register setting
+using two writes implement the bit toggling using read-modify-write.
+
+Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Acked-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/freescale/pinctrl-mxs.c | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
++++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
+@@ -195,6 +195,16 @@ static int mxs_pinctrl_get_func_groups(s
+ return 0;
+ }
+
++static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
++{
++ u32 tmp;
++
++ tmp = readl(reg);
++ tmp &= ~(mask << shift);
++ tmp |= value << shift;
++ writel(tmp, reg);
++}
++
+ static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+ {
+@@ -212,8 +222,7 @@ static int mxs_pinctrl_set_mux(struct pi
+ reg += bank * 0x20 + pin / 16 * 0x10;
+ shift = pin % 16 * 2;
+
+- writel(0x3 << shift, reg + CLR);
+- writel(g->muxsel[i] << shift, reg + SET);
++ mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
+ }
+
+ return 0;
+@@ -280,8 +289,7 @@ static int mxs_pinconf_group_set(struct
+ /* mA */
+ if (config & MA_PRESENT) {
+ shift = pin % 8 * 4;
+- writel(0x3 << shift, reg + CLR);
+- writel(ma << shift, reg + SET);
++ mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
+ }
+
+ /* vol */
--- /dev/null
+From 3908632fb829d73317c64c3d04f584b49f62e4ae Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Wed, 29 Mar 2017 21:36:51 +0300
+Subject: pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal
+
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+
+commit 3908632fb829d73317c64c3d04f584b49f62e4ae upstream.
+
+The R8A7791 PFC driver was apparently based on the preliminary revisions
+of the user's manual, which omitted the DVC_MUTE signal altogether in
+the PFC section. The modern manual has the signal described, so just add
+the necassary data to the driver...
+
+Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+@@ -206,7 +206,7 @@ enum {
+
+ /* IPSR6 */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+- FN_SCIF_CLK, FN_BPFCLK_E,
++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
+ FN_SCIFA2_RXD, FN_FMIN_E,
+ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
+@@ -576,7 +576,7 @@ enum {
+
+ /* IPSR6 */
+ AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
+- SCIF_CLK_MARK, BPFCLK_E_MARK,
++ SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
+ AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
+ SCIFA2_RXD_MARK, FMIN_E_MARK,
+ AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
+@@ -1093,6 +1093,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
+ PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
++ PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
+ PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
+ PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
+ PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
+@@ -5696,7 +5697,7 @@ static const struct pinmux_cfg_reg pinmu
+ 0, 0,
+ /* IP6_2_0 [3] */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+- FN_SCIF_CLK, 0, FN_BPFCLK_E,
++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
--- /dev/null
+From 58439280f84e6b39fd7d61f25ab30489c1aaf0a9 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Thu, 30 Mar 2017 23:20:48 +0300
+Subject: pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux data
+
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+
+commit 58439280f84e6b39fd7d61f25ab30489c1aaf0a9 upstream.
+
+PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong
+1st argument -- most probably a result of cut&paste programming...
+
+Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+@@ -1102,7 +1102,7 @@ static const u16 pinmux_data[] = {
+ PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
+ PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
+- PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
++ PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
+ PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
--- /dev/null
+From 3091ae775fae17084013021d01513bc1ad274e6a Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Thu, 9 Mar 2017 19:20:48 +0100
+Subject: pinctrl: sh-pfc: Update info pointer after SoC-specific init
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+commit 3091ae775fae17084013021d01513bc1ad274e6a upstream.
+
+Update the sh_pfc_soc_info pointer after calling the SoC-specific
+initialization function, as it may have been updated to e.g. handle
+different SoC revisions. This makes sure the correct subdriver name is
+printed later.
+
+Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sh-pfc/core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/pinctrl/sh-pfc/core.c
++++ b/drivers/pinctrl/sh-pfc/core.c
+@@ -543,6 +543,9 @@ static int sh_pfc_probe(struct platform_
+ ret = info->ops->init(pfc);
+ if (ret < 0)
+ return ret;
++
++ /* .init() may have overridden pfc->info */
++ info = pfc->info;
+ }
+
+ /* Enable dummy states for those platforms without pinctrl support */
--- /dev/null
+From 7903d4f5e1dec53963cba9b1bc472a76a3532e07 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Mon, 22 May 2017 14:25:49 +0800
+Subject: pinctrl: sunxi: Fix SPDIF function name for A83T
+
+From: Chen-Yu Tsai <wens@csie.org>
+
+commit 7903d4f5e1dec53963cba9b1bc472a76a3532e07 upstream.
+
+We use well known standard names for functions that have name, such as
+I2C, SPI, SPDIF, etc..
+
+Fix the function name of SPDIF, which was named OWA (One Wire Audio)
+based on Allwinner datasheets.
+
+Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller
+ support")
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+@@ -394,7 +394,7 @@ static const struct sunxi_desc_pin sun8i
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x3, "owa")), /* DOUT */
++ SUNXI_FUNCTION(0x3, "spdif")), /* DOUT */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
usb-usbip-set-buffer-pointers-to-null-after-free.patch
usb-fix-typo-in-the-definition-of-endpointrequest.patch
mac80211_hwsim-replace-bogus-hrtimer-clockid.patch
+sysctl-don-t-print-negative-flag-for-proc_douintvec.patch
+sysctl-report-einval-if-value-is-larger-than-uint_max-for-proc_douintvec.patch
+pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch
+pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch
+pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch
+pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch
+pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch
+pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch
--- /dev/null
+From 5380e5644afbba9e3d229c36771134976f05c91e Mon Sep 17 00:00:00 2001
+From: Liping Zhang <zlpnobody@gmail.com>
+Date: Fri, 7 Apr 2017 23:51:06 +0800
+Subject: sysctl: don't print negative flag for proc_douintvec
+
+From: Liping Zhang <zlpnobody@gmail.com>
+
+commit 5380e5644afbba9e3d229c36771134976f05c91e upstream.
+
+I saw some very confusing sysctl output on my system:
+ # cat /proc/sys/net/core/xfrm_aevent_rseqth
+ -2
+ # cat /proc/sys/net/core/xfrm_aevent_etime
+ -10
+ # cat /proc/sys/net/ipv4/tcp_notsent_lowat
+ -4294967295
+
+Because we forget to set the *negp flag in proc_douintvec, so it will
+become a garbage value.
+
+Since the value related to proc_douintvec is always an unsigned integer,
+so we can set *negp to false explictily to fix this issue.
+
+Fixes: e7d316a02f68 ("sysctl: handle error writing UINT_MAX to u32 fields")
+Signed-off-by: Liping Zhang <zlpnobody@gmail.com>
+Cc: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ kernel/sysctl.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/kernel/sysctl.c
++++ b/kernel/sysctl.c
+@@ -2070,6 +2070,7 @@ static int do_proc_douintvec_conv(bool *
+ *valp = *lvalp;
+ } else {
+ unsigned int val = *valp;
++ *negp = false;
+ *lvalp = (unsigned long)val;
+ }
+ return 0;
--- /dev/null
+From 425fffd886bae3d127a08fa6a17f2e31e24ed7ff Mon Sep 17 00:00:00 2001
+From: Liping Zhang <zlpnobody@gmail.com>
+Date: Fri, 7 Apr 2017 23:51:07 +0800
+Subject: sysctl: report EINVAL if value is larger than UINT_MAX for proc_douintvec
+
+From: Liping Zhang <zlpnobody@gmail.com>
+
+commit 425fffd886bae3d127a08fa6a17f2e31e24ed7ff upstream.
+
+Currently, inputting the following command will succeed but actually the
+value will be truncated:
+
+ # echo 0x12ffffffff > /proc/sys/net/ipv4/tcp_notsent_lowat
+
+This is not friendly to the user, so instead, we should report error
+when the value is larger than UINT_MAX.
+
+Fixes: e7d316a02f68 ("sysctl: handle error writing UINT_MAX to u32 fields")
+Signed-off-by: Liping Zhang <zlpnobody@gmail.com>
+Cc: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Cc: Eric W. Biederman <ebiederm@xmission.com>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ kernel/sysctl.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/kernel/sysctl.c
++++ b/kernel/sysctl.c
+@@ -2067,6 +2067,8 @@ static int do_proc_douintvec_conv(bool *
+ if (write) {
+ if (*negp)
+ return -EINVAL;
++ if (*lvalp > UINT_MAX)
++ return -EINVAL;
+ *valp = *lvalp;
+ } else {
+ unsigned int val = *valp;
projects / thirdparty / kernel / stable-queue.git / commitdiff
