]> git.ipfire.org Git - thirdparty/glibc.git/commitdiff
<sys/platform/x86.h>: Add CMPCCXADD support
authorH.J. Lu <hjl.tools@gmail.com>
Wed, 5 Apr 2023 16:21:35 +0000 (09:21 -0700)
committerH.J. Lu <hjl.tools@gmail.com>
Wed, 5 Apr 2023 21:46:10 +0000 (14:46 -0700)
Add CMPCCXADD support to <sys/platform/x86.h>.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
manual/platform.texi
sysdeps/x86/bits/platform/x86.h
sysdeps/x86/cpu-features.c
sysdeps/x86/include/cpu-features.h
sysdeps/x86/tst-get-cpu-features.c

index be04194c884a4381418360c80101da9b90862e21..e4d2c00886320865c8ae93db06ff8bbf17e180fc 100644 (file)
@@ -294,6 +294,9 @@ extensions.
 @item
 @code{CMOV} -- Conditional Move instructions.
 
+@item
+@code{CMPCCXADD} -- CMPccXADD instruction.
+
 @item
 @code{CMPXCHG16B} -- CMPXCHG16B instruction.
 
index c9ee8fcf90a9516308b20a5f3ed0420fecf5b329..0187964aba3bdf903a5645bec71ad5ef01bf5ef4 100644 (file)
@@ -292,6 +292,7 @@ enum
   x86_cpu_AVX_VNNI             = x86_cpu_index_7_ecx_1_eax + 4,
   x86_cpu_AVX512_BF16          = x86_cpu_index_7_ecx_1_eax + 5,
   x86_cpu_LASS                 = x86_cpu_index_7_ecx_1_eax + 6,
+  x86_cpu_CMPCCXADD            = x86_cpu_index_7_ecx_1_eax + 7,
   x86_cpu_FZLRM                        = x86_cpu_index_7_ecx_1_eax + 10,
   x86_cpu_FSRS                 = x86_cpu_index_7_ecx_1_eax + 11,
   x86_cpu_FSRCS                        = x86_cpu_index_7_ecx_1_eax + 12,
index e591e55a8854c0f9d54900becb14ad517ff9ad34..da04ad0b004ae77ed73b9b14dd8e9f356a3afffb 100644 (file)
@@ -100,6 +100,7 @@ update_active (struct cpu_features *cpu_features)
   CPU_FEATURE_SET_ACTIVE (cpu_features, RDTSCP);
   CPU_FEATURE_SET_ACTIVE (cpu_features, WBNOINVD);
   CPU_FEATURE_SET_ACTIVE (cpu_features, RAO_INT);
+  CPU_FEATURE_SET_ACTIVE (cpu_features, CMPCCXADD);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FZLRM);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRS);
   CPU_FEATURE_SET_ACTIVE (cpu_features, FSRCS);
index b946a88ad1bad099cf73d07b234b7991279318f1..4e40fe048237f37c75220fca63c52d2df7af48a1 100644 (file)
@@ -305,6 +305,7 @@ enum
 #define bit_cpu_RAO_INT                (1u << 3)
 #define bit_cpu_AVX_VNNI       (1u << 4)
 #define bit_cpu_AVX512_BF16    (1u << 5)
+#define bit_cpu_CMPCCXADD      (1u << 7)
 #define bit_cpu_FZLRM          (1u << 10)
 #define bit_cpu_FSRS           (1u << 11)
 #define bit_cpu_FSRCS          (1u << 12)
@@ -541,6 +542,7 @@ enum
 #define index_cpu_RAO_INT      CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX_VNNI     CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX512_BF16  CPUID_INDEX_7_ECX_1
+#define index_cpu_CMPCCXADD    CPUID_INDEX_7_ECX_1
 #define index_cpu_FZLRM                CPUID_INDEX_7_ECX_1
 #define index_cpu_FSRS         CPUID_INDEX_7_ECX_1
 #define index_cpu_FSRCS                CPUID_INDEX_7_ECX_1
@@ -777,6 +779,7 @@ enum
 #define reg_RAO_INT            eax
 #define reg_AVX_VNNI           eax
 #define reg_AVX512_BF16                eax
+#define reg_CMPCCXADD          eax
 #define reg_FZLRM              eax
 #define reg_FSRS               eax
 #define reg_FSRCS              eax
index 9da561a559642ec459abab416bda7aefde233ea2..d8bc92560f269368382f3dc7d34837636bb0c35a 100644 (file)
@@ -204,6 +204,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AVX_VNNI);
   CHECK_CPU_FEATURE_PRESENT (AVX512_BF16);
   CHECK_CPU_FEATURE_PRESENT (LASS);
+  CHECK_CPU_FEATURE_PRESENT (CMPCCXADD);
   CHECK_CPU_FEATURE_PRESENT (FZLRM);
   CHECK_CPU_FEATURE_PRESENT (FSRS);
   CHECK_CPU_FEATURE_PRESENT (FSRCS);
@@ -370,6 +371,7 @@ do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (RAO_INT);
   CHECK_CPU_FEATURE_ACTIVE (AVX_VNNI);
   CHECK_CPU_FEATURE_ACTIVE (AVX512_BF16);
+  CHECK_CPU_FEATURE_ACTIVE (CMPCCXADD);
   CHECK_CPU_FEATURE_ACTIVE (FZLRM);
   CHECK_CPU_FEATURE_ACTIVE (FSRS);
   CHECK_CPU_FEATURE_ACTIVE (FSRCS);