2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com>

    gcc/
    * doc/sourcebuild.texi (arm_acq_rel): Document new effective target.

    gcc/testsuite/
    * lib/target-supports.exp (check_effective_target_arm_acq_rel): New
    procedure.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237002 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8eb0cd587e48bbfca5360609cbe79d71adb5fb3a..45ae2f9eabe90ab90f8079ed16e03436e1936fb0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2016-06-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * doc/sourcebuild.texi (arm_acq_rel): Document new effective target.
+
 2016-06-01  Eduard Sanou  <dhole@openmailbox.org>
 
        * doc/cppenv.texi: Note that the `%s` in `date` is a non-standard

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 41657b5ea47dca7526d0b323e0e27580d50fe51d..0c03920cbec090b07f2559d6471c6eac9bb0c18a 100644 (file)
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1597,6 +1597,9 @@ ARM target supports executing ARMv8.1 Adv.SIMD instructions.  Some
 multilibs may be incompatible with the options needed.  Implies
 arm_v8_1a_neon_ok.
 
+@item arm_acq_rel
+ARM target supports acquire-release instructions.
+
 @item arm_prefer_ldrd_strd
 ARM target prefers @code{LDRD} and @code{STRD} instructions over
 @code{LDM} and @code{STM} instructions.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 497a2151a13699c7ccc04aea3138b606b4cf13a8..5bc66767f446990542172ca5e2ccb85d0f912751 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * lib/target-supports.exp (check_effective_target_arm_acq_rel): New
+       procedure.
+
 2016-06-01  Eduard Sanou  <dhole@openmailbox.org>
 
        * gcc.dg/cpp/source_date_epoch-1.c: New file, test the proper

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 04ca17656f2f26dda710e8a0f9ca77dd963ab39b..f4cb276ed97eaf0f809b2c221f465747320d9a03 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3494,6 +3494,25 @@ proc check_effective_target_arm_neonv2 { } {
     }
 }
 
+# Return 1 if this is an ARM target with load acquire and store release
+# instructions for 8-, 16- and 32-bit types.
+
+proc check_effective_target_arm_acq_rel { } {
+    return [check_no_compiler_messages arm_acq_rel object {
+       void
+       load_acquire_store_release (void)
+       {
+         asm ("lda r0, [r1]\n\t"
+              "stl r0, [r1]\n\t"
+              "ldah r0, [r1]\n\t"
+              "stlh r0, [r1]\n\t"
+              "ldab r0, [r1]\n\t"
+              "stlb r0, [r1]"
+              : : : "r0", "memory");
+       }
+    }]
+}
+
 # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
 # the Loongson vector modes.
 
@@ -5725,6 +5744,8 @@ proc check_effective_target_sync_int_long { } {
             || [istarget aarch64*-*-*]
             || [istarget alpha*-*-*] 
             || [istarget arm*-*-linux-*] 
+            || ([istarget arm*-*-*]
+                && [check_effective_target_arm_acq_rel])
             || [istarget bfin*-*linux*]
             || [istarget hppa*-*linux*]
             || [istarget s390*-*-*] 
@@ -5758,6 +5779,8 @@ proc check_effective_target_sync_char_short { } {
             || [istarget i?86-*-*] || [istarget x86_64-*-*]
             || [istarget alpha*-*-*] 
             || [istarget arm*-*-linux-*] 
+            || ([istarget arm*-*-*]
+                && [check_effective_target_arm_acq_rel])
             || [istarget hppa*-*linux*]
             || [istarget s390*-*-*] 
             || [istarget powerpc*-*-*]