--- /dev/null
+From 14cb5d83068ecf15d2da6f7d0e9ea9edbcbc0457 Mon Sep 17 00:00:00 2001
+From: Andrew Cooper <andrew.cooper3@citrix.com>
+Date: Fri, 7 Mar 2025 00:28:46 +0000
+Subject: x86/amd_nb: Use rdmsr_safe() in amd_get_mmconfig_range()
+
+From: Andrew Cooper <andrew.cooper3@citrix.com>
+
+commit 14cb5d83068ecf15d2da6f7d0e9ea9edbcbc0457 upstream.
+
+Xen doesn't offer MSR_FAM10H_MMIO_CONF_BASE to all guests. This results
+in the following warning:
+
+ unchecked MSR access error: RDMSR from 0xc0010058 at rIP: 0xffffffff8101d19f (xen_do_read_msr+0x7f/0xa0)
+ Call Trace:
+ xen_read_msr+0x1e/0x30
+ amd_get_mmconfig_range+0x2b/0x80
+ quirk_amd_mmconfig_area+0x28/0x100
+ pnp_fixup_device+0x39/0x50
+ __pnp_add_device+0xf/0x150
+ pnp_add_device+0x3d/0x100
+ pnpacpi_add_device_handler+0x1f9/0x280
+ acpi_ns_get_device_callback+0x104/0x1c0
+ acpi_ns_walk_namespace+0x1d0/0x260
+ acpi_get_devices+0x8a/0xb0
+ pnpacpi_init+0x50/0x80
+ do_one_initcall+0x46/0x2e0
+ kernel_init_freeable+0x1da/0x2f0
+ kernel_init+0x16/0x1b0
+ ret_from_fork+0x30/0x50
+ ret_from_fork_asm+0x1b/0x30
+
+based on quirks for a "PNP0c01" device. Treating MMCFG as disabled is the
+right course of action, so no change is needed there.
+
+This was most likely exposed by fixing the Xen MSR accessors to not be
+silently-safe.
+
+Fixes: 3fac3734c43a ("xen/pv: support selecting safe/unsafe msr accesses")
+Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Link: https://lore.kernel.org/r/20250307002846.3026685-1-andrew.cooper3@citrix.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/amd_nb.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -342,7 +342,6 @@ bool __init early_is_amd_nb(u32 device)
+
+ struct resource *amd_get_mmconfig_range(struct resource *res)
+ {
+- u32 address;
+ u64 base, msr;
+ unsigned int segn_busn_bits;
+
+@@ -350,13 +349,11 @@ struct resource *amd_get_mmconfig_range(
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+ return NULL;
+
+- /* assume all cpus from fam10h have mmconfig */
+- if (boot_cpu_data.x86 < 0x10)
++ /* Assume CPUs from Fam10h have mmconfig, although not all VMs do */
++ if (boot_cpu_data.x86 < 0x10 ||
++ rdmsrl_safe(MSR_FAM10H_MMIO_CONF_BASE, &msr))
+ return NULL;
+
+- address = MSR_FAM10H_MMIO_CONF_BASE;
+- rdmsrl(address, msr);
+-
+ /* mmconfig is not enabled */
+ if (!(msr & FAM10H_MMIO_CONF_ENABLE))
+ return NULL;