arm64: dts: qcom: sm6375: Add CPUCP L3 node

Configure the L3 cache DVFS scaler within the CPUCP block to allow
for dynamic frequency switching.

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index b768b767604f2692a839d634114d14ecd7f3fd07..a5dde682ede0de258cdbc9cc90ab8dabe1304dde 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -1513,6 +1513,15 @@
                        };
                };
 
+               cpucp_l3: interconnect@fd90000 {
+                       compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
+                       reg = <0 0x0fd90000 0 0x1000>;
+
+                       clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+                       #interconnect-cells = <1>;
+               };
+
                cpufreq_hw: cpufreq@fd91000 {
                        compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
                        reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;