int apx_usable = 0;
/* Check if KL is usable. */
int has_kl = 0;
+ /* Record AVX10 version. */
+ int avx10_set = 0;
+ int version = 0;
if ((ecx & bit_OSXSAVE))
{
/* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and
{
if (eax & bit_AVX512BF16)
set_feature (FEATURE_AVX512BF16);
+ /* AVX10 has the same XSTATE with AVX512. */
+ if (edx & bit_AVX10)
+ avx10_set = 1;
}
if (amx_usable)
{
}
}
+ /* Get Advanced Features at level 0x24 (eax = 0x24). */
+ if (avx10_set && max_cpuid_level >= 0x24)
+ {
+ __cpuid (0x24, eax, ebx, ecx, edx);
+ version = ebx & 0xff;
+ if (ebx & bit_AVX10_256)
+ switch (version)
+ {
+ case 1:
+ set_feature (FEATURE_AVX10_1_256);
+ break;
+ default:
+ set_feature (FEATURE_AVX10_1_256);
+ break;
+ }
+ if (ebx & bit_AVX10_512)
+ switch (version)
+ {
+ case 1:
+ set_feature (FEATURE_AVX10_1_512);
+ break;
+ default:
+ set_feature (FEATURE_AVX10_1_512);
+ break;
+ }
+ }
+
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
#define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
+#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
+#define OPTION_MASK_ISA2_AVX10_1_512_SET \
+ (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
#define OPTION_MASK_ISA2_AVX2_UNSET \
(OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
| OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
- | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
+ | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
+ | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
#define OPTION_MASK_ISA_AVX512F_UNSET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
#define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
+#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
+ (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
+#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BITALG_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
}
return true;
+ case OPT_mavx10_1_256:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+ opts->x_ix86_no_avx10_1_explicit = 1;
+ }
+ return true;
+
+ case OPT_mavx10_1_512:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+ opts->x_ix86_no_avx10_1_explicit = 1;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
FEATURE_SM4,
FEATURE_APX_F,
FEATURE_USER_MSR,
+ FEATURE_AVX10_1_256,
+ FEATURE_AVX10_1_512,
CPU_FEATURE_MAX
};
ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
+ ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
+ ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1-256")
+ ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, "-mavx10.1-512")
ISA_NAMES_TABLE_END
#define bit_AVXVNNIINT16 (1 << 10)
#define bit_PREFETCHI (1 << 14)
#define bit_USER_MSR (1 << 15)
+#define bit_AVX10 (1 << 19)
#define bit_APX_F (1 << 21)
/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
#define bit_AESKLE ( 1<<0 )
#define bit_WIDEKL ( 1<<2 )
+/* AVX10 sub leaf (%eax == 0x24) */
+/* %ebx */
+#define bit_AVX10_256 (1 << 17)
+#define bit_AVX10_512 (1 << 18)
/* Signatures for different CPU implementations as returned in uses
of cpuid with level 0. */
return describe_cache (level1, level2);
}
+/* Extended features */
+#define has_feature(f) \
+ has_cpu_feature (&cpu_model, cpu_features2, f)
+
+/* We will emit a warning when using AVX10.1 and AVX512 options with one
+ enabled and the other disabled. Add this function to avoid push "-mno-"
+ options under this scenario for -march=native. */
+
+bool check_avx10_avx512_features (__processor_model &cpu_model,
+ unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES],
+ const enum processor_features feature)
+{
+ if (has_feature (FEATURE_AVX512F)
+ && ((feature == FEATURE_AVX10_1_256)
+ || (feature == FEATURE_AVX10_1_512)))
+ return false;
+
+ if (has_feature (FEATURE_AVX10_1_256)
+ && ((feature == FEATURE_AVX512F)
+ || (feature == FEATURE_AVX512CD)
+ || (feature == FEATURE_AVX512DQ)
+ || (feature == FEATURE_AVX512BW)
+ || (feature == FEATURE_AVX512VL)
+ || (feature == FEATURE_AVX512IFMA)
+ || (feature == FEATURE_AVX512VBMI)
+ || (feature == FEATURE_AVX512VBMI2)
+ || (feature == FEATURE_AVX512VNNI)
+ || (feature == FEATURE_AVX512VPOPCNTDQ)
+ || (feature == FEATURE_AVX512BITALG)
+ || (feature == FEATURE_AVX512FP16)
+ || (feature == FEATURE_AVX512BF16)))
+ return false;
+
+ return true;
+}
+
/* This will be called by the spec parser in gcc.cc when it sees
a %:local_cpu_detect(args) construct. Currently it will be
called with either "arch [32|64]" or "tune [32|64]" as argument
}
}
- /* Extended features */
-#define has_feature(f) \
- has_cpu_feature (&cpu_model, cpu_features2, f)
-
if (vendor == VENDOR_AMD)
{
unsigned int name;
options = concat (options, " ",
isa_names_table[i].option, NULL);
}
- else
+ else if (check_avx10_avx512_features (cpu_model, cpu_features2,
+ isa_names_table[i].feature))
options = concat (options, neg_option,
isa_names_table[i].option + 2, NULL);
}
DEF_PTA(SM4)
DEF_PTA(APX_F)
DEF_PTA(USER_MSR)
+DEF_PTA(EVEX512)
+DEF_PTA(AVX10_1_256)
+DEF_PTA(AVX10_1_512)
{ "-msha512", OPTION_MASK_ISA2_SHA512 },
{ "-msm4", OPTION_MASK_ISA2_SM4 },
{ "-mevex512", OPTION_MASK_ISA2_EVEX512 },
- { "-musermsr", OPTION_MASK_ISA2_USER_MSR }
+ { "-musermsr", OPTION_MASK_ISA2_USER_MSR },
+ { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 },
+ { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 }
};
static struct ix86_target_opts isa_opts[] =
{
ptr->x_ix86_apx_features = opts->x_ix86_apx_features;
ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit;
ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit;
+ ptr->x_ix86_no_avx512_explicit = opts->x_ix86_no_avx512_explicit;
+ ptr->x_ix86_no_avx10_1_explicit = opts->x_ix86_no_avx10_1_explicit;
ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit;
ptr->x_ix86_arch_string = opts->x_ix86_arch_string;
ptr->x_ix86_tune_string = opts->x_ix86_tune_string;
opts->x_ix86_apx_features = ptr->x_ix86_apx_features;
opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit;
+ opts->x_ix86_no_avx512_explicit = ptr->x_ix86_no_avx512_explicit;
+ opts->x_ix86_no_avx10_1_explicit = ptr->x_ix86_no_avx10_1_explicit;
opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit;
opts->x_ix86_arch_string = ptr->x_ix86_arch_string;
opts->x_ix86_tune_string = ptr->x_ix86_tune_string;
IX86_ATTR_ISA ("apxf", OPT_mapxf),
IX86_ATTR_ISA ("evex512", OPT_mevex512),
IX86_ATTR_ISA ("usermsr", OPT_musermsr),
+ IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256),
+ IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
+ IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
target_clone_attr))
return error_mark_node;
+ /* AVX10.1-256 will enable only 256 bit AVX512F features by setting all
+ AVX512 related ISA flags and not setting EVEX512. When it is used
+ with avx512 related function attribute, we need to enable 512 bit to
+ align with the command line behavior. Manually set EVEX512 for this
+ scenario. */
+ if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
+ && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
+ && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
+
/* If the changed options are different from the default, rerun
ix86_option_override_internal, and then save the options away.
The string options are attribute options, and will be undone
|| option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
|| option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
|| enum_opts_set.x_ix86_fpmath
- || enum_opts_set.x_prefer_vector_width_type)
+ || enum_opts_set.x_prefer_vector_width_type
+ || (!(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_1_256)
+ && (opts->x_ix86_isa_flags2_explicit
+ & OPTION_MASK_ISA2_AVX10_1_256)))
{
/* If we are using the default tune= or arch=, undo the string assigned,
and use the default. */
struct gcc_options *opts_set)
{
unsigned int i;
- unsigned HOST_WIDE_INT ix86_arch_mask;
+ unsigned HOST_WIDE_INT ix86_arch_mask, avx512_isa_flags, avx512_isa_flags2;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
/* -mrecip options. */
{ "vec-sqrt", RECIP_MASK_VEC_SQRT },
};
+ avx512_isa_flags = OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD
+ | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW
+ | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA
+ | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2
+ | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ
+ | OPTION_MASK_ISA_AVX512BITALG;
+ avx512_isa_flags2 = OPTION_MASK_ISA2_AVX512FP16
+ | OPTION_MASK_ISA2_AVX512BF16;
/* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
&= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
& ~opts->x_ix86_isa_flags_explicit);
- /* Set EVEX512 target if it is not explicitly set
- when AVX512 is enabled. */
- if (TARGET_AVX512F_P(opts->x_ix86_isa_flags)
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
+ /* Emit a warning if AVX10.1 options is used with AVX512/EVEX512 options except
+ for the following option combinations:
+ 1. Both AVX10.1-512 and AVX512 with 512 bit vector width are enabled with no
+ explicit disable on other AVX512 features.
+ 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with no
+ explicit disable on other AVX512 features.
+ 3. Both AVX10.1 and AVX512 are disabled. */
+ if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2))
+ {
+ if (opts->x_ix86_no_avx512_explicit
+ && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
+ & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
+ || ((~((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
+ & opts->x_ix86_isa_flags2)
+ & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
+ & opts->x_ix86_isa_flags2_explicit)))))
+ warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable "
+ "AVX10 instructions when AVX10.1-512 is available");
+ }
+ else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
+ {
+ if (TARGET_EVEX512_P (opts->x_ix86_isa_flags2)
+ && (OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit))
+ {
+ if (!TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ || !(OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
+ {
+ /* We should not emit 512 bit instructions under AVX10.1-256
+ when EVEX512 is enabled w/o any AVX512 features enabled.
+ Disable EVEX512 bit for this. */
+ warning (0, "Using %<-mevex512%> without any AVX512 features "
+ "enabled together with AVX10.1 only will not enable "
+ "any AVX512 or AVX10.1-512 features, using 256 as "
+ "max vector size");
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512;
+ }
+ else
+ warning (0, "Vector size conflicts between AVX10.1 and AVX512, "
+ "using 512 as max vector size");
+ }
+ else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && !(OPTION_MASK_ISA2_EVEX512
+ & opts->x_ix86_isa_flags2_explicit))
+ warning (0, "Vector size conflicts between AVX10.1 and AVX512, using "
+ "512 as max vector size");
+ else if (opts->x_ix86_no_avx512_explicit
+ && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
+ & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
+ || ((~(avx512_isa_flags2 & opts->x_ix86_isa_flags2)
+ & (avx512_isa_flags2
+ & opts->x_ix86_isa_flags2_explicit)))))
+ warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions "
+ "when AVX10 is available");
+ }
+ else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
+ {
+ if (opts->x_ix86_no_avx10_1_explicit
+ && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
+ & opts->x_ix86_isa_flags2_explicit))
+ {
+ warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> "
+ "cannot disable AVX512 instructions when "
+ "%<-mavx512XXX%>");
+ /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is
+ disabled. */
+ if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit)
+ {
+ opts->x_ix86_isa_flags = (~avx512_isa_flags
+ & opts->x_ix86_isa_flags)
+ | (avx512_isa_flags & opts->x_ix86_isa_flags_explicit);
+ opts->x_ix86_isa_flags2 = (~avx512_isa_flags
+ & opts->x_ix86_isa_flags2)
+ | (avx512_isa_flags2 & opts->x_ix86_isa_flags2_explicit);
+ }
+ }
+ }
+
+ /* Set EVEX512 if one of the following conditions meets:
+ 1. AVX512 is enabled while EVEX512 is not explicitly set/unset.
+ 2. AVX10.1-512 is enabled. */
+ if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2)
+ || (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
+ /* Enable all AVX512 related ISAs when AVX10.1 is enabled. */
+ if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
+ {
+ opts->x_ix86_isa_flags |= avx512_isa_flags;
+ opts->x_ix86_isa_flags2 |= avx512_isa_flags2;
+ }
+
/* Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. */
if (!TARGET_EVEX512_P(opts->x_ix86_isa_flags2))
{
constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
- | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
+ | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_EVEX512;
constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
| PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
| PTA_RDPID | PTA_AVX512VPOPCNTDQ;
Variable
HOST_WIDE_INT ix86_isa_flags2_explicit
+; Indicate if AVX512 and AVX10.1 are explicitly set no.
+Variable
+int ix86_no_avx512_explicit = 0
+
+Variable
+int ix86_no_avx10_1_explicit = 0
+
; Additional target flags
Variable
int ix86_target_flags
TargetSave
HOST_WIDE_INT x_ix86_isa_flags_explicit
+;; which flags were passed by the user
+TargetSave
+HOST_WIDE_INT x_ix86_no_avx512_explicit
+
+;; which flags were passed by the user
+TargetSave
+HOST_WIDE_INT x_ix86_no_avx10_1_explicit
+
;; whether -mtune was not specified
TargetSave
unsigned char tune_defaulted
musermsr
Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save
Support USER_MSR built-in functions and code generation.
+
+mavx10.1-256
+Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1 built-in functions and code generation.
+
+mavx10.1-512
+Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1-512 built-in functions and code generation.
+
+mavx10.1
+Target Alias(mavx10.1-256)
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1 built-in functions and code generation.
@itemx no-usermsr
Enable/disable the generation of the USER_MSR instructions.
+@cindex @code{target("avx10.1")} function attribute, x86
+@item avx10.1
+@itemx no-avx10.1
+Enable/disable the generation of the AVX10.1 instructions.
+
+@cindex @code{target("avx10.1-256")} function attribute, x86
+@item avx10.1-256
+@itemx no-avx10.1-256
+Enable/disable the generation of the AVX10.1 instructions.
+
+@cindex @code{target("avx10.1-512")} function attribute, x86
+@item avx10.1-512
+@itemx no-avx10.1-512
+Enable/disable the generation of the AVX10.1 512 bit instructions.
+
@cindex @code{target("cld")} function attribute, x86
@item cld
@itemx no-cld
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@need 200
@opindex musermsr
@itemx -musermsr
+@need 200
+@opindex mavx10.1
+@itemx -mavx10.1
+@need 200
+@opindex mavx10.1-256
+@itemx -mavx10.1-256
+@need 200
+@opindex mavx10.1-512
+@itemx -mavx10.1-512
These switches enable the use of instructions in the MMX, SSE,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR or CLDEMOTE
-extended instruction sets. Each has a corresponding @option{-mno-} option
-to disable use of these instructions.
+AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR, AVX10.1 or
+CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-}
+option to disable use of these instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and
@item avx_runtime
Target supports the execution of @code{avx} instructions.
+@item avx10.1
+Target supports the execution of @code{avx10.1} instructions.
+
+@item avx10.1-256
+Target supports the execution of @code{avx10.1} instructions.
+
+@item avx10.1-512
+Target supports the execution of @code{avx10.1-512} instructions.
+
@item avx2
Target supports compiling @code{avx2} instructions.
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+
+#include <immintrin.h>
+
+void
+f1 ()
+{
+ register __m256d a __asm ("ymm17");
+ register __m256d b __asm ("ymm16");
+ a = _mm256_add_pd (a, b);
+ asm volatile ("" : "+v" (a));
+}
+
+void
+f2 ()
+{
+ register __m128d a __asm ("xmm17");
+ register __m128d b __asm ("xmm16");
+ a = _mm_add_pd (a, b);
+ asm volatile ("" : "+v" (a));
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f -mno-evex512" } */
+/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512 -mno-avx512f" } */
+/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
+/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx512f"))) __m512d
+foo ()
+{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1"))) __m512d
+foo ()
+{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx512f,no-evex512"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1-512"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("no-avx10.1"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("no-avx512f"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx512f"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__m512d
+foo ()
+{
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mno-avx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1-512"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */
+/* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+#include "avx10_1-2.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("evex512"))) __m512d
+foo ()
+{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1"))) __m512d
+foo ()
+{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+
+#include <immintrin.h>
+
+int
+foo (int c)
+{
+ register int a __asm ("k7") = c;
+ int b = foo (a);
+ asm volatile ("" : "+k" (b));
+ return b;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-512" } */
+
+#include <immintrin.h>
+
+long long
+foo (long long c)
+{
+ register long long a __asm ("k7") = c;
+ long long b = foo (a);
+ asm volatile ("" : "+k" (b));
+ return b;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-final { scan-assembler-not ".%zmm" } } */
+
+#include "avx10_1-2.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+
+#include <immintrin.h>
+
+long long
+foo (long long c)
+{
+ register long long a __asm ("k7") = c;
+ long long b = foo (a);
+ asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */
+ return b;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
+
+#include "avx10_1-1.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */
+/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
projects / thirdparty / gcc.git / commitdiff
