--- /dev/null
+From 0d3a1beecfa54b938edf3ed046902f072e1e180a Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao@intel.com>
+Date: Mon, 19 Jul 2010 09:43:13 +0100
+Subject: drm/i915: Always use the fixed panel timing for eDP
+
+From: Zhao Yakui <yakui.zhao@intel.com>
+
+commit 0d3a1beecfa54b938edf3ed046902f072e1e180a upstream.
+
+Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
+index 2b99ab2..233e6fd 100644
+--- a/drivers/gpu/drm/i915/intel_dp.c
++++ b/drivers/gpu/drm/i915/intel_dp.c
+@@ -511,11 +511,37 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
+ {
+ struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
+ struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
++ struct drm_device *dev = encoder->dev;
++ struct drm_i915_private *dev_priv = dev->dev_private;
+ int lane_count, clock;
+ int max_lane_count = intel_dp_max_lane_count(intel_encoder);
+ int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
+ static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+
++ if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
++ dev_priv->panel_fixed_mode) {
++ struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
++
++ adjusted_mode->hdisplay = fixed_mode->hdisplay;
++ adjusted_mode->hsync_start = fixed_mode->hsync_start;
++ adjusted_mode->hsync_end = fixed_mode->hsync_end;
++ adjusted_mode->htotal = fixed_mode->htotal;
++
++ adjusted_mode->vdisplay = fixed_mode->vdisplay;
++ adjusted_mode->vsync_start = fixed_mode->vsync_start;
++ adjusted_mode->vsync_end = fixed_mode->vsync_end;
++ adjusted_mode->vtotal = fixed_mode->vtotal;
++
++ adjusted_mode->clock = fixed_mode->clock;
++ drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
++
++ /*
++ * the mode->clock is used to calculate the Data&Link M/N
++ * of the pipe. For the eDP the fixed clock should be used.
++ */
++ mode->clock = dev_priv->panel_fixed_mode->clock;
++ }
++
+ for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
+ for (clock = 0; clock <= max_clock; clock++) {
+ int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
--- /dev/null
+From a1efd14a99483a4fb9308902397ed86b69454c99 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Mon, 12 Jul 2010 19:35:38 +0100
+Subject: drm/i915: Check overlay stride errata for i830 and i845
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit a1efd14a99483a4fb9308902397ed86b69454c99 upstream.
+
+Apparently i830 and i845 cannot handle any stride that is not a multiple
+of 256, unlike their brethren which do support 64 byte aligned strides.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_overlay.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_overlay.c
++++ b/drivers/gpu/drm/i915/intel_overlay.c
+@@ -950,7 +950,7 @@ static int check_overlay_src(struct drm_
+ || rec->src_width < N_HORIZ_Y_TAPS*4)
+ return -EINVAL;
+
+- /* check alingment constrains */
++ /* check alignment constraints */
+ switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
+ case I915_OVERLAY_RGB:
+ /* not implemented */
+@@ -982,7 +982,10 @@ static int check_overlay_src(struct drm_
+ return -EINVAL;
+
+ /* stride checking */
+- stride_mask = 63;
++ if (IS_I830(dev) || IS_845G(dev))
++ stride_mask = 255;
++ else
++ stride_mask = 63;
+
+ if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
+ return -EINVAL;
--- /dev/null
+From 1297c05a8dfb568c689f057d51a65eebe5ddc86f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed, 4 Aug 2010 11:40:00 -0400
+Subject: drm/radeon: add new pci ids
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 1297c05a8dfb568c689f057d51a65eebe5ddc86f upstream.
+
+New evergreen and r7xx ids.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ include/drm/drm_pciids.h | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -146,6 +146,8 @@
+ {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x688C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x688D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
+@@ -161,6 +163,7 @@
+ {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x68c7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+@@ -174,6 +177,7 @@
+ {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x68f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+@@ -314,6 +318,7 @@
+ {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x945E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -324,6 +329,7 @@
+ {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x948A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -366,6 +372,7 @@
+ {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9557, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x955f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
--- /dev/null
+From 4c70b2eae371ebe83019ac47de6088b78124ab36 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon, 2 Aug 2010 19:39:15 -0400
+Subject: drm/radeon/kms/igp: sideport is AMD only
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 4c70b2eae371ebe83019ac47de6088b78124ab36 upstream.
+
+Intel variants don't support it.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 15 ++++++---------
+ drivers/gpu/drm/radeon/radeon_combios.c | 4 ++++
+ drivers/gpu/drm/radeon/rs600.c | 1 -
+ drivers/gpu/drm/radeon/rs690.c | 2 +-
+ 4 files changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -1024,21 +1024,18 @@ bool radeon_atombios_sideport_present(st
+ u8 frev, crev;
+ u16 data_offset;
+
++ /* sideport is AMD only */
++ if (rdev->family == CHIP_RS600)
++ return false;
++
+ if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+ &frev, &crev, &data_offset)) {
+ igp_info = (union igp_info *)(mode_info->atom_context->bios +
+ data_offset);
+ switch (crev) {
+ case 1:
+- /* AMD IGPS */
+- if ((rdev->family == CHIP_RS690) ||
+- (rdev->family == CHIP_RS740)) {
+- if (igp_info->info.ulBootUpMemoryClock)
+- return true;
+- } else {
+- if (igp_info->info.ucMemoryType & 0xf0)
+- return true;
+- }
++ if (igp_info->info.ulBootUpMemoryClock)
++ return true;
+ break;
+ case 2:
+ if (igp_info->info_2.ucMemoryType & 0x0f)
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -693,6 +693,10 @@ bool radeon_combios_sideport_present(str
+ struct drm_device *dev = rdev->ddev;
+ u16 igp_info;
+
++ /* sideport is AMD only */
++ if (rdev->family == CHIP_RS400)
++ return false;
++
+ igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
+
+ if (igp_info) {
+--- a/drivers/gpu/drm/radeon/rs600.c
++++ b/drivers/gpu/drm/radeon/rs600.c
+@@ -475,7 +475,6 @@ void rs600_mc_init(struct radeon_device
+ rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+ base = RREG32_MC(R_000004_MC_FB_LOCATION);
+ base = G_000004_MC_FB_START(base) << 16;
+- rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+ radeon_vram_location(rdev, &rdev->mc, base);
+ radeon_gtt_location(rdev, &rdev->mc);
+ radeon_update_bandwidth_info(rdev);
+--- a/drivers/gpu/drm/radeon/rs690.c
++++ b/drivers/gpu/drm/radeon/rs690.c
+@@ -158,8 +158,8 @@ void rs690_mc_init(struct radeon_device
+ rdev->mc.visible_vram_size = rdev->mc.aper_size;
+ base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
+ base = G_000100_MC_FB_START(base) << 16;
+- rs690_pm_info(rdev);
+ rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
++ rs690_pm_info(rdev);
+ radeon_vram_location(rdev, &rdev->mc, base);
+ radeon_gtt_location(rdev, &rdev->mc);
+ radeon_update_bandwidth_info(rdev);
--- /dev/null
+From 812d046915f48236657f02c06d7dc47140e9ceda Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon, 26 Jul 2010 18:51:53 -0400
+Subject: drm/radeon/kms/r7xx: add workaround for hw issue with HDP flush
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 812d046915f48236657f02c06d7dc47140e9ceda upstream.
+
+Use of HDP_*_COHERENCY_FLUSH_CNTL can cause a hang in certain
+situations. Add workaround.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/r600.c | 24 ++++++++++++++++++++++--
+ drivers/gpu/drm/radeon/r600d.h | 1 +
+ drivers/gpu/drm/radeon/rv770.c | 5 ++++-
+ drivers/gpu/drm/radeon/rv770d.h | 1 +
+ 4 files changed, 28 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/r600.c
++++ b/drivers/gpu/drm/radeon/r600.c
+@@ -361,7 +361,17 @@ void r600_pcie_gart_tlb_flush(struct rad
+ u32 tmp;
+
+ /* flush hdp cache so updates hit vram */
+- WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
++ if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
++ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
++ u32 tmp;
++
++ /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
++ * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
++ */
++ WREG32(HDP_DEBUG1, 0);
++ tmp = readl((void __iomem *)ptr);
++ } else
++ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+
+ WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+@@ -2949,5 +2959,15 @@ int r600_debugfs_mc_info_init(struct rad
+ */
+ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
+ {
+- WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
++ /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
++ * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
++ */
++ if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
++ void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
++ u32 tmp;
++
++ WREG32(HDP_DEBUG1, 0);
++ tmp = readl((void __iomem *)ptr);
++ } else
++ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+ }
+--- a/drivers/gpu/drm/radeon/r600d.h
++++ b/drivers/gpu/drm/radeon/r600d.h
+@@ -245,6 +245,7 @@
+ #define HDP_NONSURFACE_SIZE 0x2C0C
+ #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+ #define HDP_TILING_CONFIG 0x2F3C
++#define HDP_DEBUG1 0x2F34
+
+ #define MC_VM_AGP_TOP 0x2184
+ #define MC_VM_AGP_BOT 0x2188
+--- a/drivers/gpu/drm/radeon/rv770.c
++++ b/drivers/gpu/drm/radeon/rv770.c
+@@ -174,7 +174,10 @@ static void rv770_mc_program(struct rade
+ WREG32((0x2c20 + j), 0x00000000);
+ WREG32((0x2c24 + j), 0x00000000);
+ }
+- WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
++ /* r7xx hw bug. Read from HDP_DEBUG1 rather
++ * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
++ */
++ tmp = RREG32(HDP_DEBUG1);
+
+ rv515_mc_stop(rdev, &save);
+ if (r600_mc_wait_for_idle(rdev)) {
+--- a/drivers/gpu/drm/radeon/rv770d.h
++++ b/drivers/gpu/drm/radeon/rv770d.h
+@@ -128,6 +128,7 @@
+ #define HDP_NONSURFACE_SIZE 0x2C0C
+ #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
+ #define HDP_TILING_CONFIG 0x2F3C
++#define HDP_DEBUG1 0x2F34
+
+ #define MC_SHARED_CHMAP 0x2004
+ #define NOOFCHAN_SHIFT 12
gfs2-rename-causes-kernel-oops.patch
kvm-mmu-flush-remote-tlbs-when-overwriting-spte-with-different-pfn.patch
xen-drop-xen_sched_clock-in-favour-of-using-plain-wallclock-time.patch
+drm-radeon-kms-igp-sideport-is-amd-only.patch
+drm-radeon-add-new-pci-ids.patch
+drm-radeon-kms-r7xx-add-workaround-for-hw-issue-with-hdp-flush.patch
+drm-i915-check-overlay-stride-errata-for-i830-and-i845.patch
+drm-i915-always-use-the-fixed-panel-timing-for-edp.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
