]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
target/ppc: 405: Add missing MSR_ME bit
authorFabiano Rosas <farosas@linux.ibm.com>
Fri, 28 Jan 2022 12:15:03 +0000 (13:15 +0100)
committerCédric Le Goater <clg@kaod.org>
Fri, 28 Jan 2022 12:15:03 +0000 (13:15 +0100)
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/ppc/cpu_init.c

index e63705b1c6b2d3506c2e02c1f35b1938fbde8ea5..23a13036b2116862812c7a23d59ef5217168cfaf 100644 (file)
@@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
                     (1ull << MSR_EE) |
                     (1ull << MSR_PR) |
                     (1ull << MSR_FP) |
+                    (1ull << MSR_ME) |
                     (1ull << MSR_DWE) |
                     (1ull << MSR_DE) |
                     (1ull << MSR_IR) |