[riscv] Use load and store pseudo-instructions where possible

The pattern of "load address to register" followed by "load value from
address in register" generally results in three instructions: two to
load the address and one to load the value.

This can be reduced to two instructions by allowing the assembler to
incorporate the low bits of the address within the load (or store)
instruction itself.  In the case of a store, this requires specifying
a second register that can be temporarily used to hold the high bits
of the address.  (In the case of a load, the destination register is
reused for this purpose.)

Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/arch/riscv/prefix/libprefix.S b/src/arch/riscv/prefix/libprefix.S
index fffedd82461295f09eb07bdf5605e4b268aa521f..92b7cc8fe0b99bbd1d140b751aab4fb1cced3934 100644 (file)
--- a/src/arch/riscv/prefix/libprefix.S
+++ b/src/arch/riscv/prefix/libprefix.S
@@ -257,8 +257,7 @@ apply_relocs:
        la      a2, _edata
 
        /* Calculate relocation addend */
-       la      t0, prefix_virt
-       LOADN   a0, (t0)
+       LOADN   a0, prefix_virt
        sub     a0, a1, a0
 
        /* Skip applying relocations if addend is zero */
@@ -523,8 +522,7 @@ enable_paging_64:
        li      a1, SATP_MODE_SV57
 
        /* Calculate virtual address offset */
-       la      t0, prefix_virt
-       LOADN   t0, (t0)
+       LOADN   t0, prefix_virt
        la      t1, _prefix
        sub     a0, t1, t0
 
@@ -567,8 +565,7 @@ enable_paging_64_loop:
        STOREN  t0, -PTE_SIZE(a4)
 
        /* Calculate PTE[x] address for iPXE virtual address map */
-       la      t0, prefix_virt
-       LOADN   t0, (t0)
+       LOADN   t0, prefix_virt
        srli    t0, t0, VPN1_LSB
        andi    t0, t0, ( PTE_COUNT - 1 )
        slli    t0, t0, PTE_SIZE_LOG2
@@ -711,8 +708,7 @@ enable_paging_32:
        mv      a2, a0
 
        /* Calculate virtual address offset */
-       la      t0, prefix_virt
-       LOADN   t0, (t0)
+       LOADN   t0, prefix_virt
        la      t1, _prefix
        sub     a0, t1, t0
 

diff --git a/src/arch/riscv/prefix/sbiprefix.S b/src/arch/riscv/prefix/sbiprefix.S
index 34766d53a16829d091011ee3b4880ed85e83f920..6bddc9db7a8dd3bb1e255b39f4c5b3b0ceaf1b98 100644 (file)
--- a/src/arch/riscv/prefix/sbiprefix.S
+++ b/src/arch/riscv/prefix/sbiprefix.S
@@ -79,8 +79,7 @@ _sbi_start:
        progress " .stack"
 
        /* Store boot hart */
-       la      t0, boot_hart
-       STOREN  s0, (t0)
+       STOREN  s0, boot_hart, t0
 
        /* Register device tree */
        la      a0, sysfdt