--- /dev/null
+From 9ceace3c9c18c67676e75141032a65a8e01f9a7a Mon Sep 17 00:00:00 2001
+From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
+Date: Thu, 23 Nov 2017 20:07:00 +0530
+Subject: ALSA: hda: Add Raven PCI ID
+
+From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
+
+commit 9ceace3c9c18c67676e75141032a65a8e01f9a7a upstream.
+
+This commit adds PCI ID for Raven platform
+
+Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/pci/hda/hda_intel.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/sound/pci/hda/hda_intel.c
++++ b/sound/pci/hda/hda_intel.c
+@@ -2463,6 +2463,9 @@ static const struct pci_device_id azx_id
+ /* AMD Hudson */
+ { PCI_DEVICE(0x1022, 0x780d),
+ .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
++ /* AMD Raven */
++ { PCI_DEVICE(0x1022, 0x15e3),
++ .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
+ /* ATI HDMI */
+ { PCI_DEVICE(0x1002, 0x0002),
+ .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
--- /dev/null
+From 6a468d5990ecd1c2d07dd85f8633bbdd0ba61c40 Mon Sep 17 00:00:00 2001
+From: Josef Bacik <jbacik@fb.com>
+Date: Mon, 6 Nov 2017 16:11:58 -0500
+Subject: nbd: don't start req until after the dead connection logic
+
+From: Josef Bacik <jbacik@fb.com>
+
+commit 6a468d5990ecd1c2d07dd85f8633bbdd0ba61c40 upstream.
+
+We can end up sleeping for a while waiting for the dead timeout, which
+means we could get the per request timer to fire. We did handle this
+case, but if the dead timeout happened right after we submitted we'd
+either tear down the connection or possibly requeue as we're handling an
+error and race with the endio which can lead to panics and other
+hilarity.
+
+Fixes: 560bc4b39952 ("nbd: handle dead connections")
+Signed-off-by: Josef Bacik <jbacik@fb.com>
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/block/nbd.c | 20 +++++++-------------
+ 1 file changed, 7 insertions(+), 13 deletions(-)
+
+--- a/drivers/block/nbd.c
++++ b/drivers/block/nbd.c
+@@ -288,15 +288,6 @@ static enum blk_eh_timer_return nbd_xmit
+ cmd->status = BLK_STS_TIMEOUT;
+ return BLK_EH_HANDLED;
+ }
+-
+- /* If we are waiting on our dead timer then we could get timeout
+- * callbacks for our request. For this we just want to reset the timer
+- * and let the queue side take care of everything.
+- */
+- if (!completion_done(&cmd->send_complete)) {
+- nbd_config_put(nbd);
+- return BLK_EH_RESET_TIMER;
+- }
+ config = nbd->config;
+
+ if (config->num_connections > 1) {
+@@ -740,6 +731,7 @@ static int nbd_handle_cmd(struct nbd_cmd
+ if (!refcount_inc_not_zero(&nbd->config_refs)) {
+ dev_err_ratelimited(disk_to_dev(nbd->disk),
+ "Socks array is empty\n");
++ blk_mq_start_request(req);
+ return -EINVAL;
+ }
+ config = nbd->config;
+@@ -748,6 +740,7 @@ static int nbd_handle_cmd(struct nbd_cmd
+ dev_err_ratelimited(disk_to_dev(nbd->disk),
+ "Attempted send on invalid socket\n");
+ nbd_config_put(nbd);
++ blk_mq_start_request(req);
+ return -EINVAL;
+ }
+ cmd->status = BLK_STS_OK;
+@@ -771,6 +764,7 @@ again:
+ */
+ sock_shutdown(nbd);
+ nbd_config_put(nbd);
++ blk_mq_start_request(req);
+ return -EIO;
+ }
+ goto again;
+@@ -781,6 +775,7 @@ again:
+ * here so that it gets put _after_ the request that is already on the
+ * dispatch list.
+ */
++ blk_mq_start_request(req);
+ if (unlikely(nsock->pending && nsock->pending != req)) {
+ blk_mq_requeue_request(req, true);
+ ret = 0;
+@@ -793,10 +788,10 @@ again:
+ ret = nbd_send_cmd(nbd, cmd, index);
+ if (ret == -EAGAIN) {
+ dev_err_ratelimited(disk_to_dev(nbd->disk),
+- "Request send failed trying another connection\n");
++ "Request send failed, requeueing\n");
+ nbd_mark_nsock_dead(nbd, nsock, 1);
+- mutex_unlock(&nsock->tx_lock);
+- goto again;
++ blk_mq_requeue_request(req, true);
++ ret = 0;
+ }
+ out:
+ mutex_unlock(&nsock->tx_lock);
+@@ -820,7 +815,6 @@ static blk_status_t nbd_queue_rq(struct
+ * done sending everything over the wire.
+ */
+ init_completion(&cmd->send_complete);
+- blk_mq_start_request(bd->rq);
+
+ /* We can be called directly from the user space process, which means we
+ * could possibly have signals pending so our sendmsg will fail. In
--- /dev/null
+From ff57dc94faec023abc267cdc45766fccff497557 Mon Sep 17 00:00:00 2001
+From: Josef Bacik <jbacik@fb.com>
+Date: Mon, 6 Nov 2017 16:11:57 -0500
+Subject: nbd: wait uninterruptible for the dead timeout
+
+From: Josef Bacik <jbacik@fb.com>
+
+commit ff57dc94faec023abc267cdc45766fccff497557 upstream.
+
+If we have a pending signal or the user kills their application then
+it'll bring down the whole device, which is less than awesome. Instead
+wait uninterruptible for the dead timeout so we're sure we gave it our
+best shot.
+
+Fixes: 560bc4b39952 ("nbd: handle dead connections")
+Signed-off-by: Josef Bacik <jbacik@fb.com>
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/block/nbd.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/block/nbd.c
++++ b/drivers/block/nbd.c
+@@ -723,9 +723,9 @@ static int wait_for_reconnect(struct nbd
+ return 0;
+ if (test_bit(NBD_DISCONNECTED, &config->runtime_flags))
+ return 0;
+- wait_event_interruptible_timeout(config->conn_wait,
+- atomic_read(&config->live_connections),
+- config->dead_conn_timeout);
++ wait_event_timeout(config->conn_wait,
++ atomic_read(&config->live_connections),
++ config->dead_conn_timeout);
+ return atomic_read(&config->live_connections);
+ }
+
--- /dev/null
+From 0d63785c6b94b5d2f095f90755825f90eea791f5 Mon Sep 17 00:00:00 2001
+From: Simon Guinot <simon.guinot@sequanux.org>
+Date: Mon, 13 Nov 2017 16:27:02 +0100
+Subject: net: mvneta: fix handling of the Tx descriptor counter
+
+From: Simon Guinot <simon.guinot@sequanux.org>
+
+commit 0d63785c6b94b5d2f095f90755825f90eea791f5 upstream.
+
+The mvneta controller provides a 8-bit register to update the pending
+Tx descriptor counter. Then, a maximum of 255 Tx descriptors can be
+added at once. In the current code the mvneta_txq_pend_desc_add function
+assumes the caller takes care of this limit. But it is not the case. In
+some situations (xmit_more flag), more than 255 descriptors are added.
+When this happens, the Tx descriptor counter register is updated with a
+wrong value, which breaks the whole Tx queue management.
+
+This patch fixes the issue by allowing the mvneta_txq_pend_desc_add
+function to process more than 255 Tx descriptors.
+
+Fixes: 2a90f7e1d5d0 ("net: mvneta: add xmit_more support")
+Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/ethernet/marvell/mvneta.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -816,11 +816,14 @@ static void mvneta_txq_pend_desc_add(str
+ {
+ u32 val;
+
+- /* Only 255 descriptors can be added at once ; Assume caller
+- * process TX desriptors in quanta less than 256
+- */
+- val = pend_desc + txq->pending;
+- mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
++ pend_desc += txq->pending;
++
++ /* Only 255 Tx descriptors can be added at once */
++ do {
++ val = min(pend_desc, 255);
++ mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
++ pend_desc -= val;
++ } while (pend_desc > 0);
+ txq->pending = 0;
+ }
+
--- /dev/null
+From f2ddaf8dfd4a5071ad09074d2f95ab85d35c8a1e Mon Sep 17 00:00:00 2001
+From: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com>
+Date: Tue, 17 Oct 2017 05:47:39 -0700
+Subject: PCI: Apply Cavium ThunderX ACS quirk to more Root Ports
+
+From: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com>
+
+commit f2ddaf8dfd4a5071ad09074d2f95ab85d35c8a1e upstream.
+
+Extend the Cavium ThunderX ACS quirk to cover more device IDs and restrict
+it to only Root Ports.
+
+Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com>
+[bhelgaas: changelog, stable tag]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4212,6 +4212,19 @@ static int pci_quirk_amd_sb_acs(struct p
+ #endif
+ }
+
++static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
++{
++ /*
++ * Effectively selects all downstream ports for whole ThunderX 1
++ * family by 0xf800 mask (which represents 8 SoCs), while the lower
++ * bits of device ID are used to indicate which subdevice is used
++ * within the SoC.
++ */
++ return (pci_is_pcie(dev) &&
++ (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
++ ((dev->device & 0xf800) == 0xa000));
++}
++
+ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+ /*
+@@ -4224,7 +4237,7 @@ static int pci_quirk_cavium_acs(struct p
+ */
+ acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
+
+- if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))
++ if (!pci_quirk_cavium_acs_match(dev))
+ return -ENOTTY;
+
+ return acs_flags ? 0 : 1;
--- /dev/null
+From 94ac327e043ee40d7fc57b54541da50507ef4e99 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Mon, 13 Nov 2017 08:50:30 -0600
+Subject: PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit 94ac327e043ee40d7fc57b54541da50507ef4e99 upstream.
+
+Every Port that supports the L1.2 substate advertises its Port
+Common_Mode_Restore_Time, i.e., the time the Port requires to re-establish
+common mode when exiting L1.2 (see PCIe r3.1, sec 7.33.2).
+
+Per sec 5.5.3.3.1, when exiting L1.2, the Downstream Port (the device at
+the upstream end of the link) must send TS1 training sequences for at least
+T(COMMONMODE) after it detects electrical idle exit on the Link. We want
+this to be long enough for both ends of the Link, so we should set it to
+the maximum of the Port Common_Mode_Restore_Time for the upstream and
+downstream components on the Link.
+
+Previously we only looked at the Port Common_Mode_Restore_Time of the
+upstream device, so if the downstream device required more time, we didn't
+program the upstream device's T(COMMONMODE) correctly.
+
+Fixes: f1f0366dd6be ("PCI/ASPM: Calculate and save the L1.2 timing parameters")
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
+Acked-by: Rajat Jain <rajatja@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/pcie/aspm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/pcie/aspm.c
++++ b/drivers/pci/pcie/aspm.c
+@@ -453,7 +453,7 @@ static void aspm_calc_l1ss_info(struct p
+
+ /* Choose the greater of the two T_cmn_mode_rstr_time */
+ val1 = (upreg->l1ss_cap >> 8) & 0xFF;
+- val2 = (upreg->l1ss_cap >> 8) & 0xFF;
++ val2 = (dwreg->l1ss_cap >> 8) & 0xFF;
+ if (val1 > val2)
+ link->l1ss.ctl1 |= val1 << 8;
+ else
--- /dev/null
+From c00054f540bf81e592e1fee709b0bdbf20f478b5 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Mon, 13 Nov 2017 15:05:50 -0600
+Subject: PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit c00054f540bf81e592e1fee709b0bdbf20f478b5 upstream.
+
+Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream)
+device using the capability pointer of the *child* (downstream) device,
+which corrupted some random word of the parent's config space.
+
+Use the parent's L1 SS capability pointer to program its
+LTR_L1.2_THRESHOLD.
+
+Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings")
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
+CC: Rajat Jain <rajatja@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/pcie/aspm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/pcie/aspm.c
++++ b/drivers/pci/pcie/aspm.c
+@@ -658,7 +658,7 @@ static void pcie_config_aspm_l1ss(struct
+ 0xFF00, link->l1ss.ctl1);
+
+ /* Program LTR L1.2 threshold in both ports */
+- pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
++ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
+ 0xE3FF0000, link->l1ss.ctl1);
+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
+ 0xE3FF0000, link->l1ss.ctl1);
--- /dev/null
+From 79aa801e899417a56863d6713f76c4e108856000 Mon Sep 17 00:00:00 2001
+From: Dexuan Cui <decui@microsoft.com>
+Date: Wed, 1 Nov 2017 20:30:53 +0000
+Subject: PCI: hv: Use effective affinity mask
+
+From: Dexuan Cui <decui@microsoft.com>
+
+commit 79aa801e899417a56863d6713f76c4e108856000 upstream.
+
+The effective_affinity_mask is always set when an interrupt is assigned in
+__assign_irq_vector() -> apic->cpu_mask_to_apicid(), e.g. for struct apic
+apic_physflat: -> default_cpu_mask_to_apicid() ->
+irq_data_update_effective_affinity(), but it looks d->common->affinity
+remains all-1's before the user space or the kernel changes it later.
+
+In the early allocation/initialization phase of an IRQ, we should use the
+effective_affinity_mask, otherwise Hyper-V may not deliver the interrupt to
+the expected CPU. Without the patch, if we assign 7 Mellanox ConnectX-3
+VFs to a 32-vCPU VM, one of the VFs may fail to receive interrupts.
+
+Tested-by: Adrian Suhov <v-adsuho@microsoft.com>
+Signed-off-by: Dexuan Cui <decui@microsoft.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Jake Oshins <jakeo@microsoft.com>
+Cc: Jork Loeser <jloeser@microsoft.com>
+Cc: Stephen Hemminger <sthemmin@microsoft.com>
+Cc: K. Y. Srinivasan <kys@microsoft.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/host/pci-hyperv.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/pci/host/pci-hyperv.c
++++ b/drivers/pci/host/pci-hyperv.c
+@@ -879,7 +879,7 @@ static void hv_irq_unmask(struct irq_dat
+ int cpu;
+ u64 res;
+
+- dest = irq_data_get_affinity_mask(data);
++ dest = irq_data_get_effective_affinity_mask(data);
+ pdev = msi_desc_to_pci_dev(msi_desc);
+ pbus = pdev->bus;
+ hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
+@@ -1042,6 +1042,7 @@ static void hv_compose_msi_msg(struct ir
+ struct hv_pci_dev *hpdev;
+ struct pci_bus *pbus;
+ struct pci_dev *pdev;
++ struct cpumask *dest;
+ struct compose_comp_ctxt comp;
+ struct tran_int_desc *int_desc;
+ struct {
+@@ -1056,6 +1057,7 @@ static void hv_compose_msi_msg(struct ir
+ int ret;
+
+ pdev = msi_desc_to_pci_dev(irq_data_get_msi_desc(data));
++ dest = irq_data_get_effective_affinity_mask(data);
+ pbus = pdev->bus;
+ hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
+ hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
+@@ -1081,14 +1083,14 @@ static void hv_compose_msi_msg(struct ir
+ switch (pci_protocol_version) {
+ case PCI_PROTOCOL_VERSION_1_1:
+ size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
+- irq_data_get_affinity_mask(data),
++ dest,
+ hpdev->desc.win_slot.slot,
+ cfg->vector);
+ break;
+
+ case PCI_PROTOCOL_VERSION_1_2:
+ size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
+- irq_data_get_affinity_mask(data),
++ dest,
+ hpdev->desc.win_slot.slot,
+ cfg->vector);
+ break;
--- /dev/null
+From 7f342678634f16795892677204366e835e450dda Mon Sep 17 00:00:00 2001
+From: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com>
+Date: Tue, 17 Oct 2017 05:47:38 -0700
+Subject: PCI: Set Cavium ACS capability quirk flags to assert RR/CR/SV/UF
+
+From: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com>
+
+commit 7f342678634f16795892677204366e835e450dda upstream.
+
+The Cavium ThunderX (CN8XXX) family of PCIe Root Ports does not advertise
+an ACS capability. However, the RTL internally implements similar
+protection as if ACS had Request Redirection, Completion Redirection,
+Source Validation, and Upstream Forwarding features enabled.
+
+Change Cavium ACS capabilities quirk flags accordingly.
+
+Fixes: b404bcfbf035 ("PCI: Add ACS quirk for all Cavium devices")
+Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com>
+[bhelgaas: tidy changelog, comment, stable tag]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4215,12 +4215,14 @@ static int pci_quirk_amd_sb_acs(struct p
+ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+ /*
+- * Cavium devices matching this quirk do not perform peer-to-peer
+- * with other functions, allowing masking out these bits as if they
+- * were unimplemented in the ACS capability.
++ * Cavium root ports don't advertise an ACS capability. However,
++ * the RTL internally implements similar protection as if ACS had
++ * Request Redirection, Completion Redirection, Source Validation,
++ * and Upstream Forwarding features enabled. Assert that the
++ * hardware implements and enables equivalent ACS functionality for
++ * these flags.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
+- PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
++ acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
+
+ if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))
+ return -ENOTTY;
--- /dev/null
+From 7978db344719dab1e56d05e6fc04aaaddcde0a5e Mon Sep 17 00:00:00 2001
+From: Tobias Jordan <Tobias.Jordan@elektrobit.com>
+Date: Wed, 4 Oct 2017 11:35:03 +0530
+Subject: PM / OPP: Add missing of_node_put(np)
+
+From: Tobias Jordan <Tobias.Jordan@elektrobit.com>
+
+commit 7978db344719dab1e56d05e6fc04aaaddcde0a5e upstream.
+
+The for_each_available_child_of_node() loop in _of_add_opp_table_v2()
+doesn't drop the reference to "np" on errors. Fix that.
+
+Fixes: 274659029c9d (PM / OPP: Add support to parse "operating-points-v2" bindings)
+Signed-off-by: Tobias Jordan <Tobias.Jordan@elektrobit.com>
+[ VK: Improved commit log. ]
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/base/power/opp/of.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/base/power/opp/of.c
++++ b/drivers/base/power/opp/of.c
+@@ -397,6 +397,7 @@ static int _of_add_opp_table_v2(struct d
+ dev_err(dev, "%s: Failed to add OPP, %d\n", __func__,
+ ret);
+ _dev_pm_opp_remove_table(opp_table, dev, false);
++ of_node_put(np);
+ goto put_opp_table;
+ }
+ }
mips-cmpxchg64-and-have_virt_cpu_accounting_gen-don-t-work-for-32-bit-smp.patch
mips-ralink-fix-mt7628-pinmux.patch
mips-ralink-fix-typo-in-mt7628-pinmux-function.patch
+net-mvneta-fix-handling-of-the-tx-descriptor-counter.patch
+nbd-wait-uninterruptible-for-the-dead-timeout.patch
+nbd-don-t-start-req-until-after-the-dead-connection-logic.patch
+pm-opp-add-missing-of_node_put-np.patch
+pci-aspm-account-for-downstream-device-s-port-common_mode_restore_time.patch
+pci-aspm-use-correct-capability-pointer-to-program-ltr_l1.2_threshold.patch
+pci-hv-use-effective-affinity-mask.patch
+pci-set-cavium-acs-capability-quirk-flags-to-assert-rr-cr-sv-uf.patch
+pci-apply-cavium-thunderx-acs-quirk-to-more-root-ports.patch
+alsa-hda-add-raven-pci-id.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
