This patch adds support for SME ZA-targeting non-widening BFloat16 instructions,
under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16".
FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that
"+sme-b16b16" enables "+sme2" and "+sve-b16b16".
Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*.
eg: sme-b16b16-1.s, sme-b16b16-1.d.
The spec for this feature and instructions is availabe here [1]:
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
* Add support for the x86 Zhaoxin PadLock RNG2 instruction.
+* Add support for AArch64 SME and SVE non-widening BFloat16 (SVE_B16B16 and
+ SME_B16B16) instructions.
+
* Add support for the x86 Intel AVX10.2 instructions.
* Add support for the x86 Intel SM4 AVX10.2 instructions.
{"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
AARCH64_FEATURE (SME_F8F32)},
{"sme-f16f16", AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME2)},
+ {"sme-b16b16", AARCH64_FEATURE (SME_B16B16),
+ AARCH64_FEATURES (2, SVE_B16B16, SME2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@tab Enable the SM3 and SM4 cryptographic extensions.
@item @code{sme} @tab @code{sve2}, @code{bf16}
@tab Enable the Scalable Matrix Extension.
+@item @code{sme-b16b16} @tab @code{sme2}, @code{sve-b16b16}
+ @tab Enable SME ZA-targeting non-widening BFloat16 instructions.
@item @code{sme-f8f16} @tab @code{sme-f8f32}
@tab Enable the SME F8F16 Extension.
@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
--- /dev/null
+#name: Test of SME2 non-widening BFloat16 instructions.
+#as: -march=armv8-a+sme-b16b16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c1e41c00 bfadd za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e47c00 bfadd za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41c07 bfadd za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41fc0 bfadd za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e41fc3 bfadd za.h\[w8, 3, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e51c00 bfadd za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e57c00 bfadd za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51c07 bfadd za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51f80 bfadd za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}
+.*: c1e51f83 bfadd za.h\[w8, 3, vgx4\], { ?z28.h-z31.h ?}
+.*: c1e41c08 bfsub za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e47c08 bfsub za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41c0f bfsub za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}
+.*: c1e41fc8 bfsub za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e41fcb bfsub za.h\[w8, 3, vgx2\], { ?z30.h-z31.h ?}
+.*: c1e51c08 bfsub za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e57c08 bfsub za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51c0f bfsub za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}
+.*: c1e51f88 bfsub za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}
+.*: c1e51f8b bfsub za.h\[w8, 3, vgx4\], { ?z28.h-z31.h ?}
+.*: c1101020 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1107020 bfmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1101027 bfmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c11013e0 bfmla za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, z0.h\[0\]
+.*: c11f1020 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h\[0\]
+.*: c1101c28 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1101428 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[3\]
+.*: c1101c2b bfmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1109020 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c110f020 bfmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109027 bfmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c11093a0 bfmla za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, z0.h\[0\]
+.*: c11f9020 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h\[0\]
+.*: c1109c28 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1109428 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[3\]
+.*: c1109c2b bfmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1601c00 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1607c00 bfmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601c07 bfmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601fe0 bfmla za.h\[w8, 0, vgx2\], { ?z31.h-z0.h ?}, z0.h
+.*: c16f1c00 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c16f1c03 bfmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c1701c00 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1707c00 bfmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701c07 bfmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701fe0 bfmla za.h\[w8, 0, vgx4\], { ?z31.h-z2.h ?}, z0.h
+.*: c17f1c00 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c17f1c03 bfmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c1e01008 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e07008 bfmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e0100f bfmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e013c8 bfmla za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, { ?z0.h-z1.h ?}
+.*: c1fe1008 bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1fe100b bfmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1e11008 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e17008 bfmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e1100f bfmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e11388 bfmla za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, { ?z0.h-z3.h ?}
+.*: c1fd1008 bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1fd100b bfmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1101030 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1107030 bfmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1101037 bfmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c11013f0 bfmls za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, z0.h\[0\]
+.*: c11f1030 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h\[0\]
+.*: c1101c38 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1101438 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[3\]
+.*: c1101c3b bfmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1109030 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c110f030 bfmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109037 bfmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c11093b0 bfmls za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, z0.h\[0\]
+.*: c11f9030 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h\[0\]
+.*: c1109c38 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1109438 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[3\]
+.*: c1109c3b bfmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1601c08 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1607c08 bfmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601c0f bfmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1601fe8 bfmls za.h\[w8, 0, vgx2\], { ?z31.h-z0.h ?}, z0.h
+.*: c16f1c08 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c16f1c0b bfmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c1701c08 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1707c08 bfmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701c0f bfmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1701fe8 bfmls za.h\[w8, 0, vgx4\], { ?z31.h-z2.h ?}, z0.h
+.*: c17f1c08 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c17f1c0b bfmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c1e01018 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e07018 bfmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e0101f bfmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1e013d8 bfmls za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, { ?z0.h-z1.h ?}
+.*: c1fe1018 bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1fe101b bfmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1e11018 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e17018 bfmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e1101f bfmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1e11398 bfmls za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, { ?z0.h-z3.h ?}
+.*: c1fd1018 bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1fd101b bfmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: 81a00008 bfmopa za0.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a00009 bfmopa za1.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a01c08 bfmopa za0.h, p7/m, p0/m, z0.h, z0.h
+.*: 81a0e008 bfmopa za0.h, p0/m, p7/m, z0.h, z0.h
+.*: 81a003e8 bfmopa za0.h, p0/m, p0/m, z31.h, z0.h
+.*: 81bf0008 bfmopa za0.h, p0/m, p0/m, z0.h, z31.h
+.*: 81afad48 bfmopa za0.h, p3/m, p5/m, z10.h, z15.h
+.*: 81b965e9 bfmopa za1.h, p1/m, p3/m, z15.h, z25.h
+.*: 81a00018 bfmops za0.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a00019 bfmops za1.h, p0/m, p0/m, z0.h, z0.h
+.*: 81a01c18 bfmops za0.h, p7/m, p0/m, z0.h, z0.h
+.*: 81a0e018 bfmops za0.h, p0/m, p7/m, z0.h, z0.h
+.*: 81a003f8 bfmops za0.h, p0/m, p0/m, z31.h, z0.h
+.*: 81bf0018 bfmops za0.h, p0/m, p0/m, z0.h, z31.h
+.*: 81afad58 bfmops za0.h, p3/m, p5/m, z10.h, z15.h
+.*: 81b965f9 bfmops za1.h, p1/m, p3/m, z15.h, z25.h
--- /dev/null
+/* BFADD. */
+bfadd za.h[w8, 0, vgx2], {z0.h - z1.h}
+bfadd za.h[w11, 0, vgx2], {z0.h - z1.h}
+bfadd za.h[w8, 7, vgx2], {z0.h - z1.h}
+bfadd za.h[w8, 0, vgx2], {z30.h - z31.h}
+bfadd za.h[w8, 3], {z30.h - z31.h}
+
+bfadd za.h[w8, 0, vgx4], {z0.h - z3.h}
+bfadd za.h[w11, 0, vgx4], {z0.h - z3.h}
+bfadd za.h[w8, 7, vgx4], {z0.h - z3.h}
+bfadd za.h[w8, 0, vgx4], {z28.h - z31.h}
+bfadd za.h[w8, 3], {z28.h - z31.h}
+
+/* BFSUB. */
+bfsub za.h[w8, 0, vgx2], {z0.h - z1.h}
+bfsub za.h[w11, 0, vgx2], {z0.h - z1.h}
+bfsub za.h[w8, 7, vgx2], {z0.h - z1.h}
+bfsub za.h[w8, 0, vgx2], {z30.h - z31.h}
+bfsub za.h[w8, 3], {z30.h - z31.h}
+
+bfsub za.h[w8, 0, vgx4], {z0.h - z3.h}
+bfsub za.h[w11, 0, vgx4], {z0.h - z3.h}
+bfsub za.h[w8, 7, vgx4], {z0.h - z3.h}
+bfsub za.h[w8, 0, vgx4], {z28.h - z31.h}
+bfsub za.h[w8, 3], {z28.h - z31.h}
+
+/* BFMLA (multiple and indexed vector). */
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[3]
+bfmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[3]
+bfmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* BFMLA (multiple and single vector). */
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+bfmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+bfmla za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+bfmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+bfmla za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* BFMLA (multiple vectors). */
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+bfmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+bfmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
+
+/* BFMLS (multiple and indexed vector). */
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[3]
+bfmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[3]
+bfmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* BFMLS (multiple and single vector). */
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+bfmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+bfmls za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+bfmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+bfmls za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* BFMLS (multiple vectors). */
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+bfmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+bfmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+bfmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
+
+/* BFMOPA. */
+bfmopa ZA0.h, p0/m, p0/m, z0.h, z0.h
+bfmopa ZA1.h, p0/m, p0/m, z0.h, z0.h
+bfmopa ZA0.h, p7/m, p0/m, z0.h, z0.h
+bfmopa ZA0.h, p0/m, p7/m, z0.h, z0.h
+bfmopa ZA0.h, p0/m, p0/m, z31.h, z0.h
+bfmopa ZA0.h, p0/m, p0/m, z0.h, z31.h
+bfmopa ZA0.h, p3/m, p5/m, z10.h, z15.h
+bfmopa ZA1.h, p1/m, p3/m, z15.h, z25.h
+
+/* BFMOPS. */
+bfmops ZA0.h, p0/m, p0/m, z0.h, z0.h
+bfmops ZA1.h, p0/m, p0/m, z0.h, z0.h
+bfmops ZA0.h, p7/m, p0/m, z0.h, z0.h
+bfmops ZA0.h, p0/m, p7/m, z0.h, z0.h
+bfmops ZA0.h, p0/m, p0/m, z31.h, z0.h
+bfmops ZA0.h, p0/m, p0/m, z0.h, z31.h
+bfmops ZA0.h, p3/m, p5/m, z10.h, z15.h
+bfmops ZA1.h, p1/m, p3/m, z15.h, z25.h
--- /dev/null
+#name: Test of invalid SME2 non-widening BFloat16 instructions.
+#as: -march=armv8-a+sme-b16b16
+#error_output: sme-b16b16-bad-1.l
--- /dev/null
+.*: Assembler messages:
+.*: Error: operand mismatch -- `bfadd za.s\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfadd za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w13,0,vgx2\],{ ?z1.h-z0.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfadd za.h\[w8,11,vgx3\],{ ?z0.h-z1.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w8,0,vgx2\],{ ?z0.h-z4.h ?}'
+.*: Error: operand mismatch -- `bfadd za.s\[w8,0,vgx4\],{ ?z0.h-z3.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfadd za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfadd za.h\[w14,0,vgx4\],{ ?z10.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfadd za.h\[w8,15,vgx1\],{ ?z3.h-z2.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfadd za.h\[w8,0,vgx4\],{ ?z30.h-z31.h ?}'
+.*: Error: operand mismatch -- `bfsub za.s\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfsub za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w13,0,vgx2\],{ ?z1.h-z0.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfsub za.h\[w8,11,vgx3\],{ ?z0.h-z1.h ?}'
+.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w8,0,vgx2\],{ ?z0.h-z4.h ?}'
+.*: Error: operand mismatch -- `bfsub za.s\[w8,0,vgx4\],{ ?z0.h-z3.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfsub za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}
+.*: Error: too many registers in vector register list at operand 2 -- `bfsub za.h\[w14,0,vgx4\],{ ?z10.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfsub za.h\[w8,15,vgx1\],{ ?z3.h-z2.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfsub za.h\[w8,0,vgx4\],{ ?z30.h-z31.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,0,vgx3\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,0,vgx3\],{ ?z31.h-z0.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z31.h-z2.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.d\[w8,15,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx3\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 3 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmla za.b\[w8,20,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 20, vgx2\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.s\[w8,15,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmla za.b\[w8,20,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmla za.h\[w8, 20, vgx4\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,0,vgx3\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,0,vgx3\],{ ?z31.h-z0.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z31.h-z2.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.d\[w8,15,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx3\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 3 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `bfmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmls za.b\[w8,20,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 20, vgx2\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.s\[w8,15,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `bfmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `bfmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `bfmls za.b\[w8,20,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: bfmls za.h\[w8, 20, vgx4\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: operand mismatch -- `bfmopa ZA1.h,p0,p0/m,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za1.h, p0/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmopa ZA0.h,p7/m,p0,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za0.h, p7/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmopa ZA0.h,p0/m,p7/m,z0.s,z0.s'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za0.h, p0/m, p7/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmopa ZA0.h,p0/m,p0/m,z31.d,z0.d'
+.*: Info: did you mean this\?
+.*: Info: bfmopa za0.h, p0/m, p0/m, z31.h, z0.h
+.*: Error: ZA tile number out of range at operand 1 -- `bfmopa ZA2.h,p0/m,p8/m,z0.s,z31.b'
+.*: Error: ZA tile number out of range at operand 1 -- `bfmopa ZA4.h,p15/m,p11/m,z0.s,z31.b'
+.*: Error: operand mismatch -- `bfmops ZA1.h,p0,p0/m,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmops za1.h, p0/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmops ZA0.h,p7/m,p0,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: bfmops za0.h, p7/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmops ZA0.h,p0/m,p7/m,z0.s,z0.s'
+.*: Info: did you mean this\?
+.*: Info: bfmops za0.h, p0/m, p7/m, z0.h, z0.h
+.*: Error: operand mismatch -- `bfmops ZA0.h,p0/m,p0/m,z31.d,z0.d'
+.*: Info: did you mean this\?
+.*: Info: bfmops za0.h, p0/m, p0/m, z31.h, z0.h
+.*: Error: ZA tile number out of range at operand 1 -- `bfmops ZA2.h,p0/m,p8/m,z0.s,z31.b'
+.*: Error: ZA tile number out of range at operand 1 -- `bfmops ZA4.h,p15/m,p11/m,z0.s,z31.b'
--- /dev/null
+/* BFADD. */
+bfadd za.s[w8, 0, vgx2], {z0.h - z1.h}
+bfadd za.h[w13, 0, vgx2], {z1.h - z0.h}
+bfadd za.h[w8, 11, vgx3], {z0.h - z1.h}
+bfadd za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+bfadd za.s[w8, 0, vgx4], {z0.h - z3.h}
+bfadd za.h[w14, 0, vgx4], {z10.h - z3.h}
+bfadd za.h[w8, 15, vgx1], {z3.h - z2.h}
+bfadd za.h[w8, 0, vgx4], {z30.h - z31.h}
+
+/* BFSUB. */
+bfsub za.s[w8, 0, vgx2], {z0.h - z1.h}
+bfsub za.h[w13, 0, vgx2], {z1.h - z0.h}
+bfsub za.h[w8, 11, vgx3], {z0.h - z1.h}
+bfsub za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+bfsub za.s[w8, 0, vgx4], {z0.h - z3.h}
+bfsub za.h[w14, 0, vgx4], {z10.h - z3.h}
+bfsub za.h[w8, 15, vgx1], {z3.h - z2.h}
+bfsub za.h[w8, 0, vgx4], {z30.h - z31.h}
+
+/* BFMLA (multiple and indexed vector). */
+bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmla za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0.h}, z0.h
+bfmla za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+bfmla za.h[w8, 0, vgx2], {z0 - z1}
+
+bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmla za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+bfmla za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+bfmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0.h}, z0.h
+bfmla za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+bfmla za.h[w8, 0, vgx4], {z0 - z1}
+
+/* BFMLA (multiple and single vector). */
+bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+bfmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+bfmla za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+bfmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+bfmla za.h[w8, 0, vgx2], {z0.h}, z15.h
+bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+bfmla za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+bfmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+bfmla za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+bfmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+bfmla za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+bfmla za.h[w8, 0, vgx4], {z0.h}, z15.h
+bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+bfmla za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* BFMLA (multiple vectors). */
+bfmla za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+bfmla za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmla za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+bfmla za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmla za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+bfmla za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmla za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+bfmla za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmla za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+bfmla za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+bfmla za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmla za.b[w8, 20, vgx4], {z0.h}, {z30.h}
+
+/* BFMLS (multiple and indexed vector). */
+bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+bfmls za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0.h}, z0.h
+bfmls za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+bfmls za.h[w8, 0, vgx2], {z0 - z1}
+
+bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+bfmls za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+bfmls za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+bfmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0.h}, z0.h
+bfmls za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+bfmls za.h[w8, 0, vgx4], {z0 - z1}
+
+/* BFMLS (multiple and single vector). */
+bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+bfmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+bfmls za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+bfmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+bfmls za.h[w8, 0, vgx2], {z0.h}, z15.h
+bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+bfmls za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+bfmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+bfmls za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+bfmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+bfmls za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+bfmls za.h[w8, 0, vgx4], {z0.h}, z15.h
+bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+bfmls za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* BFMLS (multiple vectors). */
+bfmls za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+bfmls za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+bfmls za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+bfmls za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+bfmls za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+bfmls za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmls za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+bfmls za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+bfmls za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+bfmls za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+bfmls za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+bfmls za.b[w8, 20, vgx4], {z0.h}, {z30.h}
+
+/* BFMOPA. */
+bfmopa ZA0.s, p0/m, p0/m, z0.h, z0.h
+bfmopa ZA1.h, p0, p0/m, z0.h, z0.h
+bfmopa ZA0.h, p7/m, p0, z0.h, z0.h
+bfmopa ZA0.h, p0/m, p7/m, z0.s, z0.s
+bfmopa ZA0.h, p0/m, p0/m, z31.d, z0.d
+bfmopa ZA2.h, p0/m, p8/m, z0.s, z31.b
+bfmopa ZA4.h, p15/m, p11/m, z0.s, z31.b
+
+/* BFMOPS. */
+bfmops ZA0.s, p0/m, p0/m, z0.h, z0.h
+bfmops ZA1.h, p0, p0/m, z0.h, z0.h
+bfmops ZA0.h, p7/m, p0, z0.h, z0.h
+bfmops ZA0.h, p0/m, p7/m, z0.s, z0.s
+bfmops ZA0.h, p0/m, p0/m, z31.d, z0.d
+bfmops ZA2.h, p0/m, p8/m, z0.s, z31.b
+bfmops ZA4.h, p15/m, p11/m, z0.s, z31.b
AARCH64_FEATURE_SME_F16F16,
/* SVE Z-targeting non-widening BFloat16 instructions. */
AARCH64_FEATURE_SVE_B16B16,
+ /* SME non-widening BFloat16 instructions. */
+ AARCH64_FEATURE_SME_B16B16,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
10987654321098765432109876543210
x1000000000x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3330;
+ return 3348;
}
else
{
10987654321098765432109876543210
x1000000100x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3332;
+ return 3350;
}
}
else
10987654321098765432109876543210
x1000000010x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3331;
+ return 3349;
}
else
{
10987654321098765432109876543210
x1000000110x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3333;
+ return 3351;
}
}
}
10987654321098765432109876543210
x1000000xx0x0011xxxxxx1xxxxxxxxx
movaz. */
- return 3334;
+ return 3352;
}
}
}
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3462;
+ return 3480;
}
else
{
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3463;
+ return 3481;
}
else
{
10987654321098765432109876543210
x1000000xx01101x10xxxxxxxxxxxxxx
luti4. */
- return 3327;
+ return 3345;
}
}
else
10987654321098765432109876543210
x1000000xx01101xx1xxxxxxxxxxxxxx
luti4. */
- return 3326;
+ return 3344;
}
}
}
10987654321098765432109876543210
x1000000000x011xxxxx001xxxxxxxxx
movaz. */
- return 3320;
+ return 3338;
}
else
{
10987654321098765432109876543210
x1000000100x011xxxxx001xxxxxxxxx
movaz. */
- return 3322;
+ return 3340;
}
}
else
10987654321098765432109876543210
x1000000010x011xxxxx001xxxxxxxxx
movaz. */
- return 3321;
+ return 3339;
}
else
{
10987654321098765432109876543210
x1000000110x011xxxxx001xxxxxxxxx
movaz. */
- return 3323;
+ return 3341;
}
}
}
10987654321098765432109876543210
x1000000000011000xxx00xxxxxxxxxx
zero. */
- return 3335;
+ return 3353;
}
else
{
10987654321098765432109876543210
x1000000000011100xxx00xxxxxxxxxx
zero. */
- return 3336;
+ return 3354;
}
}
else
10987654321098765432109876543210
x1000000000011010xxx00xxxxxxxxxx
zero. */
- return 3338;
+ return 3356;
}
else
{
10987654321098765432109876543210
x1000000000011110xxx00xxxxxxxxxx
zero. */
- return 3341;
+ return 3359;
}
}
}
10987654321098765432109876543210
x1000000000011001xxx00xxxxxxxxxx
zero. */
- return 3337;
+ return 3355;
}
else
{
10987654321098765432109876543210
x1000000000011101xxx00xxxxxxxxxx
zero. */
- return 3340;
+ return 3358;
}
}
else
10987654321098765432109876543210
x1000000000011011xxx00xxxxxxxxxx
zero. */
- return 3339;
+ return 3357;
}
else
{
10987654321098765432109876543210
x1000000000011111xxx00xxxxxxxxxx
zero. */
- return 3342;
+ return 3360;
}
}
}
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3464;
+ return 3482;
}
}
else
10987654321098765432109876543210
x1000000xx0111xxx0xx00xxxxxxxxxx
luti2. */
- return 3325;
+ return 3343;
}
else
{
10987654321098765432109876543210
x1000000xx0111xxx1xx00xxxxxxxxxx
luti2. */
- return 3324;
+ return 3342;
}
}
}
10987654321098765432109876543210
x1000000xx0xx11xxxxx101xxxxxxxxx
movaz. */
- return 3328;
+ return 3346;
}
}
}
10987654321098765432109876543210
x1000000000xx11xxxxx011xxxxxxxxx
movaz. */
- return 3316;
+ return 3334;
}
else
{
10987654321098765432109876543210
x1000000100xx11xxxxx011xxxxxxxxx
movaz. */
- return 3318;
+ return 3336;
}
}
else
10987654321098765432109876543210
x1000000010xx11xxxxx011xxxxxxxxx
movaz. */
- return 3317;
+ return 3335;
}
else
{
10987654321098765432109876543210
x1000000110xx11xxxxx011xxxxxxxxx
movaz. */
- return 3319;
+ return 3337;
}
}
}
10987654321098765432109876543210
x1000000xx0xx11xxxxx111xxxxxxxxx
movaz. */
- return 3329;
+ return 3347;
}
}
}
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3530;
+ return 3548;
}
else
{
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3529;
+ return 3547;
}
}
else
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3523;
+ return 3541;
}
}
}
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx00xxxx
fmla. */
- return 3345;
+ return 3363;
}
else
{
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx000xxxx
fmla. */
- return 3346;
+ return 3364;
}
else
{
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx100xxxx
fdot. */
- return 3508;
+ return 3526;
}
}
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx10xxxx
- usmlall. */
- return 2933;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx10xxxx
+ usmlall. */
+ return 2933;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx10xxxx
+ usmlall. */
+ return 2934;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx10xxxx
- usmlall. */
- return 2934;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx10xxxx
+ bfmla. */
+ return 3320;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxxx10xxxx
+ bfmla. */
+ return 3321;
+ }
}
}
}
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx01xxxx
fmls. */
- return 3351;
+ return 3369;
}
else
{
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxxx01xxxx
fmls. */
- return 3352;
+ return 3370;
}
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx11xxxx
- sumlall. */
- return 2849;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx11xxxx
+ sumlall. */
+ return 2849;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx11xxxx
+ sumlall. */
+ return 2850;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx11xxxx
- sumlall. */
- return 2850;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx11xxxx
+ bfmls. */
+ return 3326;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxxx11xxxx
+ bfmls. */
+ return 3327;
+ }
}
}
}
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3343;
+ return 3361;
}
}
else
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3522;
+ return 3540;
}
}
}
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3515;
+ return 3533;
}
}
}
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx11xxx
fmops. */
- return 3344;
+ return 3362;
}
}
else
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3514;
+ return 3532;
}
}
}
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3521;
+ return 3539;
}
else
{
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3501;
+ return 3519;
}
else
{
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3502;
+ return 3520;
}
else
{
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3513;
+ return 3531;
}
else
{
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3532;
+ return 3550;
}
else
{
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3507;
+ return 3525;
}
}
}
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3531;
+ return 3549;
}
}
}
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3533;
+ return 3551;
}
else
{
{
if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001xx1xxxxxxxxxxxxxxxx0xxxx
- fmopa. */
- return 2415;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx00xxx
+ fmopa. */
+ return 2415;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx10xxx
+ fmops. */
+ return 2418;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001xx1xxxxxxxxxxxxxxxx1xxxx
- fmops. */
- return 2418;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx01xxx
+ bfmopa. */
+ return 3332;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx11xxx
+ bfmops. */
+ return 3333;
+ }
}
}
else
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3527;
+ return 3545;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3528;
+ return 3546;
}
}
}
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3525;
+ return 3543;
}
else
{
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3526;
+ return 3544;
}
}
}
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3511;
+ return 3529;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3512;
+ return 3530;
}
}
}
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3519;
+ return 3537;
}
else
{
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3520;
+ return 3538;
}
}
}
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3517;
+ return 3535;
}
else
{
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3518;
+ return 3536;
}
}
}
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3524;
+ return 3542;
}
}
else
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3516;
+ return 3534;
}
}
else
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx111xxxxx00xxx
- fmla. */
- return 3347;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3365;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010110xxxx0xx111xxxxx00xxx
+ bfmla. */
+ return 3322;
+ }
}
else
{
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x10x1x00xx111xxxxx00xxx
- fadd. */
- return 3465;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x1x00xx111xxxxx00xxx
+ fadd. */
+ return 3483;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011110x1x00xx111xxxxx00xxx
+ bfadd. */
+ return 3316;
+ }
}
}
else
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x10x1x10xx111xxxxx00xxx
- fadd. */
- return 3466;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x1x10xx111xxxxx00xxx
+ fadd. */
+ return 3484;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011110x1x10xx111xxxxx00xxx
+ bfadd. */
+ return 3317;
+ }
}
}
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx111xxxxx00xxx
- fmla. */
- return 3348;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x011xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3366;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x111xxxx0xx111xxxxx00xxx
+ bfmla. */
+ return 3323;
+ }
}
}
}
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3505;
+ return 3523;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3506;
+ return 3524;
}
}
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx100xxxxx01xxx
- fdot. */
- return 3509;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3527;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010011xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3528;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x11xxxx0xx100xxxxx01xxx
- fdot. */
- return 3510;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx00xx100xxxxx01xxx
+ fmla. */
+ return 3367;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx100xxxxx01xxx
+ fmla. */
+ return 3368;
+ }
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx00xx100xxxxx01xxx
- fmla. */
- return 3349;
+ x1000001x11xxxx00xx100xxxxx01xxx
+ bfmla. */
+ return 3324;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxxx01xxx
- fmla. */
- return 3350;
+ x1000001x11xxxx10xx100xxxxx01xxx
+ bfmla. */
+ return 3325;
}
}
}
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx111xxxxx01xxx
- fmls. */
- return 3353;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010xxxx0xx111xxxxx01xxx
+ fmls. */
+ return 3371;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010110xxxx0xx111xxxxx01xxx
+ bfmls. */
+ return 3328;
+ }
}
else
{
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x10x1x00xx111xxxxx01xxx
- fsub. */
- return 3467;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x1x00xx111xxxxx01xxx
+ fsub. */
+ return 3485;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011110x1x00xx111xxxxx01xxx
+ bfsub. */
+ return 3318;
+ }
}
}
else
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x10x1x10xx111xxxxx01xxx
- fsub. */
- return 3468;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x1x10xx111xxxxx01xxx
+ fsub. */
+ return 3486;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011110x1x10xx111xxxxx01xxx
+ bfsub. */
+ return 3319;
+ }
}
}
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx111xxxxx01xxx
- fmls. */
- return 3354;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x011xxxx0xx111xxxxx01xxx
+ fmls. */
+ return 3372;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x111xxxx0xx111xxxxx01xxx
+ bfmls. */
+ return 3329;
+ }
}
}
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx100xxxxx11xxx
- fdot. */
- return 3503;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3521;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010011xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3522;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x11xxxx0xx100xxxxx11xxx
- fdot. */
- return 3504;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx00xx100xxxxx11xxx
+ fmls. */
+ return 3373;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx100xxxxx11xxx
+ fmls. */
+ return 3374;
+ }
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx00xx100xxxxx11xxx
- fmls. */
- return 3355;
+ x1000001x11xxxx00xx100xxxxx11xxx
+ bfmls. */
+ return 3330;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxxx11xxx
- fmls. */
- return 3356;
+ x1000001x11xxxx10xx100xxxxx11xxx
+ bfmls. */
+ return 3331;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3439;
+ return 3457;
}
}
else
10987654321098765432109876543210
x1000001101x0000111000xxxxxxxxx0
fcvt. */
- return 3357;
+ return 3375;
}
else
{
10987654321098765432109876543210
x1000001101x0000111000xxxxxxxxx1
fcvtl. */
- return 3358;
+ return 3376;
}
}
}
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3436;
+ return 3454;
}
else
{
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3431;
+ return 3449;
}
}
else
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3437;
+ return 3455;
}
}
else
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3438;
+ return 3456;
}
}
}
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3432;
+ return 3450;
}
else
{
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3433;
+ return 3451;
}
}
else
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3427;
+ return 3445;
}
else
{
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3428;
+ return 3446;
}
}
}
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3434;
+ return 3452;
}
else
{
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3435;
+ return 3453;
}
}
else
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3429;
+ return 3447;
}
else
{
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3430;
+ return 3448;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3441;
+ return 3459;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3440;
+ return 3458;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3442;
+ return 3460;
}
}
}
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3443;
+ return 3461;
}
else
{
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3444;
+ return 3462;
}
}
}
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3445;
+ return 3463;
}
else
{
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3446;
+ return 3464;
}
}
}
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3447;
+ return 3465;
}
else
{
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3449;
+ return 3467;
}
else
{
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3448;
+ return 3466;
}
else
{
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3450;
+ return 3468;
}
else
{
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3452;
+ return 3470;
}
}
else
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3451;
+ return 3469;
}
}
}
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3361;
+ return 3379;
}
else
{
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3372;
+ return 3390;
}
}
else
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3359;
+ return 3377;
}
else
{
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3363;
+ return 3381;
}
else
{
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3365;
+ return 3383;
}
}
}
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3362;
+ return 3380;
}
else
{
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3360;
+ return 3378;
}
}
}
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3364;
+ return 3382;
}
}
}
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3388;
+ return 3406;
}
else
{
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3378;
+ return 3396;
}
else
{
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3376;
+ return 3394;
}
else
{
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3373;
+ return 3391;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3379;
+ return 3397;
}
else
{
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3377;
+ return 3395;
}
}
}
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3397;
+ return 3415;
}
else
{
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3396;
+ return 3414;
}
else
{
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3398;
+ return 3416;
}
}
}
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3366;
+ return 3384;
}
else
{
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3367;
+ return 3385;
}
}
else
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3368;
+ return 3386;
}
}
}
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3369;
+ return 3387;
}
}
else
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3370;
+ return 3388;
}
}
}
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3389;
+ return 3407;
}
}
}
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3392;
+ return 3410;
}
}
else
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3399;
+ return 3417;
}
}
else
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3400;
+ return 3418;
}
}
else
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3401;
+ return 3419;
}
}
}
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3488;
+ return 3506;
}
}
else
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3490;
+ return 3508;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3500;
+ return 3518;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3486;
+ return 3504;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3491;
+ return 3509;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3487;
+ return 3505;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3492;
+ return 3510;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3493;
+ return 3511;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3489;
+ return 3507;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3496;
+ return 3514;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3499;
+ return 3517;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3485;
+ return 3503;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3494;
+ return 3512;
}
}
else
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3498;
+ return 3516;
}
}
else
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3395;
+ return 3413;
}
}
else
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3495;
+ return 3513;
}
else
{
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3497;
+ return 3515;
}
}
else
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3380;
+ return 3398;
}
else
{
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3381;
+ return 3399;
}
}
else
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3382;
+ return 3400;
}
}
else
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3383;
+ return 3401;
}
}
else
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3384;
+ return 3402;
}
else
{
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3385;
+ return 3403;
}
}
else
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3386;
+ return 3404;
}
}
else
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3387;
+ return 3405;
}
}
}
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3371;
+ return 3389;
}
else
{
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3375;
+ return 3393;
}
}
else
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3374;
+ return 3392;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3457;
+ return 3475;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3458;
+ return 3476;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3459;
+ return 3477;
}
else
{
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3460;
+ return 3478;
}
}
else
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3461;
+ return 3479;
}
}
}
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3419;
+ return 3437;
}
else
{
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3415;
+ return 3433;
}
}
else
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3420;
+ return 3438;
}
else
{
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3416;
+ return 3434;
}
}
}
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3424;
+ return 3442;
}
else
{
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3423;
+ return 3441;
}
}
else
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3425;
+ return 3443;
}
else
{
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3426;
+ return 3444;
}
}
}
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3421;
+ return 3439;
}
else
{
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3417;
+ return 3435;
}
}
else
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3422;
+ return 3440;
}
else
{
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3418;
+ return 3436;
}
}
}
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3390;
+ return 3408;
}
else
{
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3391;
+ return 3409;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3393;
+ return 3411;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3394;
+ return 3412;
}
}
else
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3453;
+ return 3471;
}
}
}
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3455;
+ return 3473;
}
else
{
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3456;
+ return 3474;
}
}
else
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3454;
+ return 3472;
}
}
}
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3477;
+ return 3495;
}
else
{
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3479;
+ return 3497;
}
}
else
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3478;
+ return 3496;
}
else
{
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3480;
+ return 3498;
}
}
}
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3410;
+ return 3428;
}
else
{
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3411;
+ return 3429;
}
}
else
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3412;
+ return 3430;
}
}
}
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3469;
+ return 3487;
}
else
{
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3471;
+ return 3489;
}
else
{
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3473;
+ return 3491;
}
else
{
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3474;
+ return 3492;
}
}
}
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3413;
+ return 3431;
}
}
}
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3406;
+ return 3424;
}
else
{
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3407;
+ return 3425;
}
}
else
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3402;
+ return 3420;
}
else
{
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3403;
+ return 3421;
}
}
}
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3408;
+ return 3426;
}
else
{
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3409;
+ return 3427;
}
}
else
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3404;
+ return 3422;
}
else
{
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3405;
+ return 3423;
}
}
}
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3414;
+ return 3432;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3470;
+ return 3488;
}
else
{
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3472;
+ return 3490;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3475;
+ return 3493;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3476;
+ return 3494;
}
}
}
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3481;
+ return 3499;
}
else
{
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3483;
+ return 3501;
}
}
else
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3482;
+ return 3500;
}
else
{
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3484;
+ return 3502;
}
}
}
AARCH64_FEATURES (2, SVE_B16B16, SVE2);
static const aarch64_feature_set aarch64_feature_sve_b16b16_sme2 =
AARCH64_FEATURES (2, SVE_B16B16, SME2);
+static const aarch64_feature_set aarch64_feature_sme_b16b16 =
+ AARCH64_FEATURES (2, SME_B16B16, SME2);
static const aarch64_feature_set aarch64_feature_sme2p1 =
AARCH64_FEATURE (SME2p1);
static const aarch64_feature_set aarch64_feature_sve2p1 =
#define D128_THE &aarch64_feature_d128_the
#define B16B16_SVE2 &aarch64_feature_sve_b16b16_sve2
#define SVE_B16B16_SME &aarch64_feature_sve_b16b16_sme2
+#define SME_B16B16 &aarch64_feature_sme_b16b16
#define SME2p1 &aarch64_feature_sme2p1
#define SVE2p1 &aarch64_feature_sve2p1
#define RCPC3 &aarch64_feature_rcpc3
#define SVE_B16B16_SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE_B16B16_SME, OPS, QUALS, \
FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
+#define SME_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SME_B16B16, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
SVE_B16B16_SME_INSN("bfclamp", 0xc120c000, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
SVE_B16B16_SME_INSN("bfclamp", 0xc120c800, 0xffe0fc03, sme_misc, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_HHH,0, 0),
+/* SME ZA-targeting non-widening BFloat16 instructions. */
+ SME_B16B16_INSN("bfadd", 0xc1e41c00, 0xffff9c38, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD(2), 0),
+ SME_B16B16_INSN("bfadd", 0xc1e51c00, 0xffff9c78, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD(4), 0),
+ SME_B16B16_INSN("bfsub", 0xc1e41c08, 0xffff9c38, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD(2), 0),
+ SME_B16B16_INSN("bfsub", 0xc1e51c08, 0xffff9c78, sme_misc, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmla", 0xc1101020, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
+ SME_B16B16_INSN("bfmla", 0xc1109020, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmla", 0xc1601c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(2), 0),
+ SME_B16B16_INSN("bfmla", 0xc1701c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmla", 0xc1e01008, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 0),
+ SME_B16B16_INSN("bfmla", 0xc1e11008, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmls", 0xc1101030, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
+ SME_B16B16_INSN("bfmls", 0xc1109030, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmls", 0xc1601c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(2), 0),
+ SME_B16B16_INSN("bfmls", 0xc1701c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmls", 0xc1e01018, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD(2), 0),
+ SME_B16B16_INSN("bfmls", 0xc1e11018, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD(4), 0),
+ SME_B16B16_INSN("bfmopa", 0x81a00008, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
+ SME_B16B16_INSN("bfmops", 0x81a00018, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
+
/* SME2.1 movaz instructions. */
SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
projects / thirdparty / binutils-gdb.git / commitdiff
